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| author |  Lioncash <mathew1800@gmail.com> | 2015-08-06 18:09:52 -0400 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-08-06 18:09:52 -0400 |
| commit | 482165224181c6c4c04bf3d42962d9caca2a814b (patch) | |
| tree | da545082e7f2c2e158f56f504ffa35e1fc986a48 /src/core/arm/disassembler/arm_disasm.h | |
| parent | b6c241d667dd6a22b1dadaf9c2d6ddaac2e93de5 (diff) | |
| parent | 3425cfe54a46512a2ef35e5254c2d32e14ace69a (diff) | |
Merge pull request #1022 from aroulin/disas-missing-v6k-instructions
Disassembler: ARMv6K instructions
Diffstat (limited to 'src/core/arm/disassembler/arm_disasm.h')
| -rw-r--r-- | src/core/arm/disassembler/arm_disasm.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h index f94bd466..d04fd21e 100644 --- a/src/core/arm/disassembler/arm_disasm.h +++ b/src/core/arm/disassembler/arm_disasm.h @@ -20,6 +20,7 @@ enum Opcode { OP_BLX, OP_BX, OP_CDP, + OP_CLREX, OP_CLZ, OP_CMN, OP_CMP, @@ -29,6 +30,10 @@ enum Opcode { OP_LDR, OP_LDRB, OP_LDRBT, + OP_LDREX, + OP_LDREXB, + OP_LDREXD, + OP_LDREXH, OP_LDRH, OP_LDRSB, OP_LDRSH, @@ -41,11 +46,13 @@ enum Opcode { OP_MSR, OP_MUL, OP_MVN, + OP_NOP, OP_ORR, OP_PLD, OP_RSB, OP_RSC, OP_SBC, + OP_SEV, OP_SMLAL, OP_SMULL, OP_STC, @@ -53,6 +60,10 @@ enum Opcode { OP_STR, OP_STRB, OP_STRBT, + OP_STREX, + OP_STREXB, + OP_STREXD, + OP_STREXH, OP_STRH, OP_STRT, OP_SUB, @@ -63,6 +74,9 @@ enum Opcode { OP_TST, OP_UMLAL, OP_UMULL, + OP_WFE, + OP_WFI, + OP_YIELD, // Define thumb opcodes OP_THUMB_UNDEFINED, @@ -117,7 +131,9 @@ class ARM_Disasm { static Opcode Decode01(uint32_t insn); static Opcode Decode10(uint32_t insn); static Opcode Decode11(uint32_t insn); + static Opcode DecodeSyncPrimitive(uint32_t insn); static Opcode DecodeMUL(uint32_t insn); + static Opcode DecodeMSRImmAndHints(uint32_t insn); static Opcode DecodeLDRH(uint32_t insn); static Opcode DecodeALU(uint32_t insn); @@ -135,7 +151,9 @@ class ARM_Disasm { static std::string DisassembleMUL(Opcode opcode, uint32_t insn); static std::string DisassembleMRS(uint32_t insn); static std::string DisassembleMSR(uint32_t insn); + static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn); static std::string DisassemblePLD(uint32_t insn); + static std::string DisassembleREX(Opcode opcode, uint32_t insn); static std::string DisassembleSWI(uint32_t insn); static std::string DisassembleSWP(Opcode opcode, uint32_t insn); }; |