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authoraroulin <andy.roulin@epfl.ch>2015-08-07 10:10:35 +0200
committeraroulin <andy.roulin@epfl.ch>2015-08-09 01:31:03 +0200
commit47657a18179c6dc3bf5fa573fd60381cbffcd9e7 (patch)
tree7cb492b330fb85618f11d1c5bd7ee8f4073154d2 /src/core/arm/disassembler/arm_disasm.h
parentf48a89af8bc76a81a1c3fc3d4c2f52a8dc3b323b (diff)
arm_disasm: ARMv6 packing and sign-extend media instructions
PKH, SEL SXTAB, SXTAB16, SXTB, SXTB16, SXTH, SXTAH UXTAB, UXTAB16, UXTB, UXTB16, UXTH, UXTAH
Diffstat (limited to 'src/core/arm/disassembler/arm_disasm.h')
-rw-r--r--src/core/arm/disassembler/arm_disasm.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h
index d04fd21e..20e92fd0 100644
--- a/src/core/arm/disassembler/arm_disasm.h
+++ b/src/core/arm/disassembler/arm_disasm.h
@@ -48,10 +48,12 @@ enum Opcode {
OP_MVN,
OP_NOP,
OP_ORR,
+ OP_PKH,
OP_PLD,
OP_RSB,
OP_RSC,
OP_SBC,
+ OP_SEL,
OP_SEV,
OP_SMLAL,
OP_SMULL,
@@ -70,10 +72,22 @@ enum Opcode {
OP_SWI,
OP_SWP,
OP_SWPB,
+ OP_SXTAB,
+ OP_SXTAB16,
+ OP_SXTAH,
+ OP_SXTB,
+ OP_SXTB16,
+ OP_SXTH,
OP_TEQ,
OP_TST,
OP_UMLAL,
OP_UMULL,
+ OP_UXTAB,
+ OP_UXTAB16,
+ OP_UXTAH,
+ OP_UXTB,
+ OP_UXTB16,
+ OP_UXTH,
OP_WFE,
OP_WFI,
OP_YIELD,
@@ -132,8 +146,10 @@ class ARM_Disasm {
static Opcode Decode10(uint32_t insn);
static Opcode Decode11(uint32_t insn);
static Opcode DecodeSyncPrimitive(uint32_t insn);
+ static Opcode DecodePackingSaturationReversal(uint32_t insn);
static Opcode DecodeMUL(uint32_t insn);
static Opcode DecodeMSRImmAndHints(uint32_t insn);
+ static Opcode DecodeMedia(uint32_t insn);
static Opcode DecodeLDRH(uint32_t insn);
static Opcode DecodeALU(uint32_t insn);
@@ -152,8 +168,11 @@ class ARM_Disasm {
static std::string DisassembleMRS(uint32_t insn);
static std::string DisassembleMSR(uint32_t insn);
static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
+ static std::string DisassemblePKH(uint32_t insn);
static std::string DisassemblePLD(uint32_t insn);
static std::string DisassembleREX(Opcode opcode, uint32_t insn);
+ static std::string DisassembleSEL(uint32_t insn);
static std::string DisassembleSWI(uint32_t insn);
static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
+ static std::string DisassembleXT(Opcode opcode, uint32_t insn);
};