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| author |  mtklein <mtklein@chromium.org> | 2015-08-24 10:32:02 -0700 |
|---|---|---|
| committer |  Commit bot <commit-bot@chromium.org> | 2015-08-24 10:32:02 -0700 |
| commit | 5141d90796034a932a48738cf76091957314c9a1 (patch) | |
| tree | a448edcc1ac205850892c907d450d0991efca42c /include/core/SkPreConfig.h | |
| parent | 26db32bc9a44aa922b4d2f4784274cd247b4890c (diff) | |
Add build targets for advanced Intel instruction sets (1 of 3).
CL (1 of 3) adds empty lists in our .gypi,
and builds the files in those empty lists with the appropriate flags.
CL (2 of 3) will have Chrome's GYP and GN files read these lists,
and build them with the appropriate flags.
CL (3 of 3) will add runtime detection and stub files to the lists
with empty Init_sse42(), Init_avx(), Init_avx2() methods.
After that, we should be able to use SSE 4.2, AVX, and AVX2 if desired.
Some motivation:
- SSE 4.2 adds some sweet string-oriented methods that
can help us write fast high quality 32-bit hashes.
- AVX is SSE doubled, e.g. 8 floats or two SkPMFloat at a time.
- AVX2 is SSE2 doubled, e.g. 8 pixels at a time.
BUG=skia:4117
Review URL: https://codereview.chromium.org/1290423007
Diffstat (limited to 'include/core/SkPreConfig.h')
| -rw-r--r-- | include/core/SkPreConfig.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/include/core/SkPreConfig.h b/include/core/SkPreConfig.h index 7a849f566e..0c720010f7 100644 --- a/include/core/SkPreConfig.h +++ b/include/core/SkPreConfig.h @@ -114,12 +114,18 @@ #define SK_CPU_SSE_LEVEL_SSSE3 31 #define SK_CPU_SSE_LEVEL_SSE41 41 #define SK_CPU_SSE_LEVEL_SSE42 42 +#define SK_CPU_SSE_LEVEL_AVX 51 +#define SK_CPU_SSE_LEVEL_AVX2 52 // Are we in GCC? #ifndef SK_CPU_SSE_LEVEL // These checks must be done in descending order to ensure we set the highest // available SSE level. - #if defined(__SSE4_2__) + #if defined(__AVX2__) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX2 + #elif defined(__AVX__) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX + #elif defined(__SSE4_2__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE42 #elif defined(__SSE4_1__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE41 @@ -136,9 +142,13 @@ #ifndef SK_CPU_SSE_LEVEL // These checks must be done in descending order to ensure we set the highest // available SSE level. 64-bit intel guarantees at least SSE2 support. - #if defined(_M_X64) || defined(_M_AMD64) - #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2 - #elif defined (_M_IX86_FP) + #if defined(__AVX2__) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX2 + #elif defined(__AVX__) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX + #elif defined(_M_X64) || defined(_M_AMD64) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2 + #elif defined(_M_IX86_FP) #if _M_IX86_FP >= 2 #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2 #elif _M_IX86_FP == 1 |