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| author |  commit-bot@chromium.org <commit-bot@chromium.org@2bbb7eff-a529-9590-31e7-b0007b416f81> | 2014-05-08 15:17:50 +0000 |
|---|---|---|
| committer | commit-bot@chromium.org <commit-bot@chromium.org@2bbb7eff-a529-9590-31e7-b0007b416f81> | 2014-05-08 15:17:50 +0000 |
| commit | 2656b1dbb37906ee9bf77e5bc64806ab60956645 (patch) | |
| tree | f69e215af09138d12d567f0d09981df1339df536 /include/core/SkPreConfig.h | |
| parent | c4f9cbd6288b06973a446289a47da25b80a94f6b (diff) | |
Improved x86 SSE build and run-time checks.
Replaces the current build/run-time checks for SSE level in
opts_check_x86.cpp with a simpler and more future-proof version.
Also adds SSE versions 4.1 and 4.2 to the config file.
Author: henrik.smiding@intel.com
Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
R=reed@google.com, mtklein@google.com, tomhudson@google.com, djsollen@google.com, joakim.landberg@intel.com
Author: henrik.smiding@intel.com
Review URL: https://codereview.chromium.org/272503006
git-svn-id: http://skia.googlecode.com/svn/trunk@14644 2bbb7eff-a529-9590-31e7-b0007b416f81
Diffstat (limited to 'include/core/SkPreConfig.h')
| -rw-r--r-- | include/core/SkPreConfig.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/include/core/SkPreConfig.h b/include/core/SkPreConfig.h index 9aefc2d64a..a15f8ecf22 100644 --- a/include/core/SkPreConfig.h +++ b/include/core/SkPreConfig.h @@ -123,12 +123,18 @@ #define SK_CPU_SSE_LEVEL_SSE2 20 #define SK_CPU_SSE_LEVEL_SSE3 30 #define SK_CPU_SSE_LEVEL_SSSE3 31 +#define SK_CPU_SSE_LEVEL_SSE41 41 +#define SK_CPU_SSE_LEVEL_SSE42 42 // Are we in GCC? #ifndef SK_CPU_SSE_LEVEL // These checks must be done in descending order to ensure we set the highest // available SSE level. - #if defined(__SSSE3__) + #if defined(__SSE4_2__) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE42 + #elif defined(__SSE4_1__) + #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE41 + #elif defined(__SSSE3__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSSE3 #elif defined(__SSE3__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE3 |