diff options
| author |  Mike Klein <mtklein@chromium.org> | 2017-02-28 14:35:03 +0000 |
|---|---|---|
| committer |  Skia Commit-Bot <skia-commit-bot@chromium.org> | 2017-02-28 16:16:11 +0000 |
| commit | 3c322e23a013e78fcbe0edd7adccd580af8466bc (patch) | |
| tree | 1e1aec67aae6a03a655a95b44ecd1944608e518a | |
| parent | c746bc15c167bc2a22169c2211fd2e65d9e266f5 (diff) | |
Add AVX-512 detection to SkCpu
I've added a SKY alias for the five new bits detected on a Skylake Xeon.
Change-Id: I9f7dd48f4dc866608d81befd061434ca325ef451
Reviewed-on: https://skia-review.googlesource.com/9043
Reviewed-by: Herb Derby <herb@google.com>
Commit-Queue: Mike Klein <mtklein@chromium.org>
| -rw-r--r-- | src/core/SkCpu.cpp | 15 | ||||
| -rw-r--r-- | src/core/SkCpu.h | 37 |
2 files changed, 38 insertions, 14 deletions
diff --git a/src/core/SkCpu.cpp b/src/core/SkCpu.cpp index 5e5b3169c7..0f89cf603e 100644 --- a/src/core/SkCpu.cpp +++ b/src/core/SkCpu.cpp @@ -49,7 +49,9 @@ if (abcd[2] & (1<<19)) { features |= SkCpu::SSE41; } if (abcd[2] & (1<<20)) { features |= SkCpu::SSE42; } - if ((abcd[2] & (3<<26)) == (3<<26) && (xgetbv(0) & 6) == 6) { // XSAVE + OSXSAVE + uint64_t xcr0 = xgetbv(0); + if ((abcd[2] & (3<<26)) == (3<<26) // XSAVE + OSXSAVE + && (xcr0 & (3<<1)) == (3<<1)) { // XMM and YMM state enabled. if (abcd[2] & (1<<28)) { features |= SkCpu:: AVX; } if (abcd[2] & (1<<29)) { features |= SkCpu::F16C; } if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; } @@ -58,6 +60,17 @@ if (abcd[1] & (1<<5)) { features |= SkCpu::AVX2; } if (abcd[1] & (1<<3)) { features |= SkCpu::BMI1; } if (abcd[1] & (1<<8)) { features |= SkCpu::BMI2; } + + if ((xcr0 & (7<<5)) == (7<<5)) { // All ZMM state bits enabled too. + if (abcd[1] & (1<<16)) { features |= SkCpu::AVX512F; } + if (abcd[1] & (1<<17)) { features |= SkCpu::AVX512DQ; } + if (abcd[1] & (1<<21)) { features |= SkCpu::AVX512IFMA; } + if (abcd[1] & (1<<26)) { features |= SkCpu::AVX512PF; } + if (abcd[1] & (1<<27)) { features |= SkCpu::AVX512ER; } + if (abcd[1] & (1<<28)) { features |= SkCpu::AVX512CD; } + if (abcd[1] & (1<<30)) { features |= SkCpu::AVX512BW; } + if (abcd[1] & (1<<31)) { features |= SkCpu::AVX512VL; } + } } return features; } diff --git a/src/core/SkCpu.h b/src/core/SkCpu.h index 34c19d2540..24428d9781 100644 --- a/src/core/SkCpu.h +++ b/src/core/SkCpu.h @@ -12,21 +12,32 @@ struct SkCpu { enum { - SSE1 = 1 << 0, - SSE2 = 1 << 1, - SSE3 = 1 << 2, - SSSE3 = 1 << 3, - SSE41 = 1 << 4, - SSE42 = 1 << 5, - AVX = 1 << 6, - F16C = 1 << 7, - FMA = 1 << 8, - AVX2 = 1 << 9, - BMI1 = 1 << 10, - BMI2 = 1 << 11, - + SSE1 = 1 << 0, + SSE2 = 1 << 1, + SSE3 = 1 << 2, + SSSE3 = 1 << 3, + SSE41 = 1 << 4, + SSE42 = 1 << 5, + AVX = 1 << 6, + F16C = 1 << 7, + FMA = 1 << 8, + AVX2 = 1 << 9, + BMI1 = 1 << 10, + BMI2 = 1 << 11, // Handy alias for all the cool Haswell+ instructions. HSW = AVX2 | BMI1 | BMI2 | F16C | FMA, + + AVX512F = 1 << 12, + AVX512DQ = 1 << 13, + AVX512IFMA = 1 << 14, + AVX512PF = 1 << 15, + AVX512ER = 1 << 16, + AVX512CD = 1 << 17, + AVX512BW = 1 << 18, + AVX512VL = 1 << 19, + + // Handy alias for all the cool Skylake Xeon+ instructions. + SKY = AVX512F | AVX512DQ | AVX512CD | AVX512BW | AVX512VL, }; enum { NEON = 1 << 0, |