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# format of a line in this file:
# <instruction name> <opcode> <args>
#
# <opcode> is given by specifying one or more range/value pairs:
# highbit..lowbit=value (e.g. 31..25=0x45 14..12=0x0)
#
# <args> follows the conventions in xcc/src/opcodes/mips-opc.c
unimp 31..0=0
j 31..27=0x18 imm27 # opcodes 0x60-0x64
jal 31..27=0x19 imm27 # opcodes 0x64-0x68
lui 31..25=0x71 ra imm20
slori 31..25=0x72 ra imm20
beq 31..25=0x73 14..12=0 ra rb imm
bne 31..25=0x73 14..12=1 ra rb imm
blt 31..25=0x73 14..12=2 ra rb imm
bltu 31..25=0x73 14..12=3 ra rb imm
ble 31..25=0x73 14..12=4 ra rb imm
bleu 31..25=0x73 14..12=5 ra rb imm
addi 31..25=0x74 14..12=0 ra rb imm
addiw 31..25=0x74 14..12=1 ra rb imm
slti 31..25=0x74 14..12=2 ra rb imm
sltiu 31..25=0x74 14..12=3 ra rb imm
andi 31..25=0x74 14..12=4 ra rb imm
ori 31..25=0x74 14..12=5 ra rb imm
xori 31..25=0x74 14..12=6 ra rb imm
add 31..25=0x75 14..12=0 11..5=0 rc rb ra
sub 31..25=0x75 14..12=0 11..5=1 rc rb ra
slt 31..25=0x75 14..12=0 11..5=2 rc rb ra
sltu 31..25=0x75 14..12=0 11..5=3 rc rb ra
and 31..25=0x75 14..12=0 11..5=4 rc rb ra
or 31..25=0x75 14..12=0 11..5=5 rc rb ra
xor 31..25=0x75 14..12=0 11..5=6 rc rb ra
nor 31..25=0x75 14..12=0 11..5=7 rc rb ra
mul 31..25=0x75 14..12=1 11..5=0 rc rb ra
mulh 31..25=0x75 14..12=1 11..5=2 rc rb ra
mulhu 31..25=0x75 14..12=1 11..5=3 rc rb ra
div 31..25=0x75 14..12=1 11..5=4 rc rb ra
divu 31..25=0x75 14..12=1 11..5=5 rc rb ra
rem 31..25=0x75 14..12=1 11..5=6 rc rb ra
remu 31..25=0x75 14..12=1 11..5=7 rc rb ra
sllv 31..25=0x75 14..12=4 11..5=1 rc rb ra
srlv 31..25=0x75 14..12=4 11..5=2 rc rb ra
srav 31..25=0x75 14..12=4 11..5=3 rc rb ra
sll 31..25=0x75 14..12=5 11=0 24..20=0 rc rb shamt
srl 31..25=0x75 14..12=6 11=0 24..20=0 rc rb shamt
sra 31..25=0x75 14..12=7 11=0 24..20=0 rc rb shamt
addw 31..25=0x76 14..12=0 11..5=0 rc rb ra
subw 31..25=0x76 14..12=0 11..5=1 rc rb ra
mulw 31..25=0x76 14..12=1 11..5=0 rc rb ra
mulhw 31..25=0x76 14..12=1 11..5=2 rc rb ra
mulhuw 31..25=0x76 14..12=1 11..5=3 rc rb ra
divw 31..25=0x76 14..12=1 11..5=4 rc rb ra
divuw 31..25=0x76 14..12=1 11..5=5 rc rb ra
remw 31..25=0x76 14..12=1 11..5=6 rc rb ra
remuw 31..25=0x76 14..12=1 11..5=7 rc rb ra
sllvw 31..25=0x76 14..12=4 11..5=1 rc rb ra
srlvw 31..25=0x76 14..12=4 11..5=2 rc rb ra
sravw 31..25=0x76 14..12=4 11..5=3 rc rb ra
sllw 31..25=0x76 14..12=5 11..10=0 24..20=0 rc rb shamtw
srlw 31..25=0x76 14..12=6 11..10=0 24..20=0 rc rb shamtw
sraw 31..25=0x76 14..12=7 11..10=0 24..20=0 rc rb shamtw
lb 31..25=0x78 14..12=0 rb ra imm
lh 31..25=0x78 14..12=1 rb ra imm
lw 31..25=0x78 14..12=2 rb ra imm
ld 31..25=0x78 14..12=3 rb ra imm
lbu 31..25=0x78 14..12=4 rb ra imm
lhu 31..25=0x78 14..12=5 rb ra imm
lwu 31..25=0x78 14..12=6 rb ra imm
synci 31..25=0x78 14..12=7 24..20=0 rb imm
sb 31..25=0x79 14..12=0 rb ra imm
sh 31..25=0x79 14..12=1 rb ra imm
sw 31..25=0x79 14..12=2 rb ra imm
sd 31..25=0x79 14..12=3 rb ra imm
l.s 31..25=0x79 14..12=4 rb ra imm
l.d 31..25=0x79 14..12=5 rb ra imm
s.s 31..25=0x79 14..12=6 rb ra imm
s.d 31..25=0x79 14..12=7 rb ra imm
jalr.c 31..25=0x7B 19..15=0 14..12=0 11..5=0 ra rc
jalr.r 31..25=0x7B 19..15=0 14..12=0 11..5=1 ra rc
jalr.j 31..25=0x7B 19..15=0 14..12=0 11..5=2 ra rc
rdpc 31..25=0x7B 24..15=0 14..12=1 11..5=0 rc
rdhwr 31..25=0x7B 19..15=0 14..12=2 11..5=0 rc ra
sync 31..25=0x7B 24..15=0 14..12=3 11..0=0
syscall 31..25=0x7B 24..15=0 14..12=4 11..0=0
break 31..25=0x7B 24..15=0 14..12=5 11..0=0
ei 31..25=0x7E 14..12=0 19..15=0 11..0=0 ra
di 31..25=0x7E 14..12=1 19..15=0 11..0=0 ra
eret 31..25=0x7E 14..12=2 24..15=0 11..0=0
mfpcr 31..25=0x7E 14..12=4 11..0=0 ra rb
mwfpcr 31..25=0x7E 14..12=5 11..0=0 ra rb
mtpcr 31..25=0x7E 14..12=6 11..0=0 ra rb
mwtpcr 31..25=0x7E 14..12=7 11..0=0 ra rb
# 0x7F is reserved for 64-bit-long instructions
add.s 31..25=0x68 14..12=0 11..10=0 9..5=0 rc rb ra
sub.s 31..25=0x68 14..12=0 11..10=0 9..5=1 rc rb ra
mul.s 31..25=0x68 14..12=0 11..10=0 9..5=2 rc rb ra
div.s 31..25=0x68 14..12=0 11..10=0 9..5=3 rc rb ra
sqrt.s 31..25=0x68 14..12=0 11..10=0 9..5=4 19..15=0 rc ra
sgninj.s 31..25=0x68 14..12=0 11..10=0 9..5=5 rc rb ra
sgninjn.s 31..25=0x68 14..12=0 11..10=0 9..5=6 rc rb ra
sgnmul.s 31..25=0x68 14..12=0 11..10=0 9..5=7 rc rb ra
add.d 31..25=0x68 14..12=0 11..10=3 9..5=0 rc rb ra
sub.d 31..25=0x68 14..12=0 11..10=3 9..5=1 rc rb ra
mul.d 31..25=0x68 14..12=0 11..10=3 9..5=2 rc rb ra
div.d 31..25=0x68 14..12=0 11..10=3 9..5=3 rc rb ra
sqrt.d 31..25=0x68 14..12=0 11..10=3 9..5=4 19..15=0 rc ra
sgninj.d 31..25=0x68 14..12=0 11..10=3 9..5=5 rc rb ra
sgninjn.d 31..25=0x68 14..12=0 11..10=3 9..5=6 rc rb ra
sgnmul.d 31..25=0x68 14..12=0 11..10=3 9..5=7 rc rb ra
trunc.l.s 31..25=0x68 14..12=1 11..10=0 9..5=0 19..15=0 rc ra
truncu.l.s 31..25=0x68 14..12=1 11..10=0 9..5=1 19..15=0 rc ra
trunc.w.s 31..25=0x68 14..12=1 11..10=0 9..5=2 19..15=0 rc ra
truncu.w.s 31..25=0x68 14..12=1 11..10=0 9..5=3 19..15=0 rc ra
trunc.l.d 31..25=0x68 14..12=1 11..10=3 9..5=0 19..15=0 rc ra
truncu.l.d 31..25=0x68 14..12=1 11..10=3 9..5=1 19..15=0 rc ra
trunc.w.d 31..25=0x68 14..12=1 11..10=3 9..5=2 19..15=0 rc ra
truncu.w.d 31..25=0x68 14..12=1 11..10=3 9..5=3 19..15=0 rc ra
cvt.s.l 31..25=0x68 14..12=1 11..10=0 9..5=4 19..15=0 rc ra
cvtu.s.l 31..25=0x68 14..12=1 11..10=0 9..5=5 19..15=0 rc ra
cvt.s.w 31..25=0x68 14..12=1 11..10=0 9..5=6 19..15=0 rc ra
cvtu.s.w 31..25=0x68 14..12=1 11..10=0 9..5=7 19..15=0 rc ra
cvt.d.l 31..25=0x68 14..12=1 11..10=3 9..5=4 19..15=0 rc ra
cvtu.d.l 31..25=0x68 14..12=1 11..10=3 9..5=5 19..15=0 rc ra
cvt.d.w 31..25=0x68 14..12=1 11..10=3 9..5=6 19..15=0 rc ra
cvtu.d.w 31..25=0x68 14..12=1 11..10=3 9..5=7 19..15=0 rc ra
cvt.s.d 31..25=0x68 14..12=1 11..10=0 9..5=0x13 19..15=0 rc ra
cvt.d.s 31..25=0x68 14..12=1 11..10=3 9..5=0x10 19..15=0 rc ra
c.eq.s 31..25=0x68 14..12=2 11..10=0 9..5=1 rc ra rb
c.lt.s 31..25=0x68 14..12=2 11..10=0 9..5=2 rc ra rb
c.le.s 31..25=0x68 14..12=2 11..10=0 9..5=3 rc ra rb
c.eq.d 31..25=0x68 14..12=2 11..10=3 9..5=1 rc ra rb
c.lt.d 31..25=0x68 14..12=2 11..10=3 9..5=2 rc ra rb
c.le.d 31..25=0x68 14..12=2 11..10=3 9..5=3 rc ra rb
mff.s 31..25=0x6A 14..12=0 11..0=0 ra rb
mff.d 31..25=0x6A 14..12=1 11..0=0 ra rb
mtf.s 31..25=0x6A 14..12=4 11..0=0 ra rb
mtf.d 31..25=0x6A 14..12=5 11..0=0 ra rb
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