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# format of a line in this file:
# <instruction name> <opcode> <args>
#
# <opcode> is given by specifying one or more range/value pairs:
# highbit..lowbit=value (e.g. 6..2=0x45 9..7=0x0)
#
# <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw
j imm25 6..2=0x19 1..0=3
jal imm25 6..2=0x1B 1..0=3
jalr.c rd rs1 imm12 9..7=0 6..2=0x1A 1..0=3
jalr.r rd rs1 imm12 9..7=1 6..2=0x1A 1..0=3
jalr.j rd rs1 imm12 9..7=2 6..2=0x1A 1..0=3
rdnpc rd 26..22=0 21..10=0 9..7=4 6..2=0x1A 1..0=3
beq imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3
bne imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3
blt imm12hi rs1 rs2 imm12lo 9..7=4 6..2=0x18 1..0=3
bge imm12hi rs1 rs2 imm12lo 9..7=5 6..2=0x18 1..0=3
bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3
bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3
lui rd imm20 6..2=0x0D 1..0=3
addi rd rs1 imm12 9..7=0 6..2=0x04 1..0=3
slli rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3
slti rd rs1 imm12 9..7=2 6..2=0x04 1..0=3
sltiu rd rs1 imm12 9..7=3 6..2=0x04 1..0=3
xori rd rs1 imm12 9..7=4 6..2=0x04 1..0=3
srli rd rs1 21..17=0 16=0 shamt 9..7=5 6..2=0x04 1..0=3
srai rd rs1 21..17=0 16=1 shamt 9..7=5 6..2=0x04 1..0=3
ori rd rs1 imm12 9..7=6 6..2=0x04 1..0=3
andi rd rs1 imm12 9..7=7 6..2=0x04 1..0=3
add rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0C 1..0=3
sub rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0C 1..0=3
sll rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0C 1..0=3
slt rd rs1 rs2 16=0 15..10=0 9..7=2 6..2=0x0C 1..0=3
sltu rd rs1 rs2 16=0 15..10=0 9..7=3 6..2=0x0C 1..0=3
xor rd rs1 rs2 16=0 15..10=0 9..7=4 6..2=0x0C 1..0=3
srl rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0C 1..0=3
sra rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0C 1..0=3
or rd rs1 rs2 16=0 15..10=0 9..7=6 6..2=0x0C 1..0=3
and rd rs1 rs2 16=0 15..10=0 9..7=7 6..2=0x0C 1..0=3
mul rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0C 1..0=3
mulh rd rs1 rs2 16=0 15..10=1 9..7=1 6..2=0x0C 1..0=3
mulhsu rd rs1 rs2 16=0 15..10=1 9..7=2 6..2=0x0C 1..0=3
mulhu rd rs1 rs2 16=0 15..10=1 9..7=3 6..2=0x0C 1..0=3
div rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0C 1..0=3
divu rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0C 1..0=3
rem rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0C 1..0=3
remu rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0C 1..0=3
addiw rd rs1 imm12 9..7=0 6..2=0x06 1..0=3
slliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=1 6..2=0x06 1..0=3
srliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
sraiw rd rs1 21..17=0 16=1 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
addw rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0E 1..0=3
subw rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0E 1..0=3
sllw rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0E 1..0=3
srlw rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0E 1..0=3
sraw rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0E 1..0=3
mulw rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0E 1..0=3
divw rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0E 1..0=3
divuw rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0E 1..0=3
remw rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0E 1..0=3
remuw rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0E 1..0=3
lb rd rs1 imm12 9..7=0 6..2=0x00 1..0=3
lh rd rs1 imm12 9..7=1 6..2=0x00 1..0=3
lw rd rs1 imm12 9..7=2 6..2=0x00 1..0=3
ld rd rs1 imm12 9..7=3 6..2=0x00 1..0=3
lbu rd rs1 imm12 9..7=4 6..2=0x00 1..0=3
lhu rd rs1 imm12 9..7=5 6..2=0x00 1..0=3
lwu rd rs1 imm12 9..7=6 6..2=0x00 1..0=3
# NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c
# and elfxx-mips.c to detect them. this is a hack to handle the split immed.
# just open up those files and search for MATCH_SW; should be obvious.
sb imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3
sh imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3
sw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3
sd imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x08 1..0=3
amoadd.w rd rs1 rs2 16..10=0 9..7=2 6..2=0x0A 1..0=3
amoswap.w rd rs1 rs2 16..10=1 9..7=2 6..2=0x0A 1..0=3
amoand.w rd rs1 rs2 16..10=2 9..7=2 6..2=0x0A 1..0=3
amoor.w rd rs1 rs2 16..10=3 9..7=2 6..2=0x0A 1..0=3
amomin.w rd rs1 rs2 16..10=4 9..7=2 6..2=0x0A 1..0=3
amomax.w rd rs1 rs2 16..10=5 9..7=2 6..2=0x0A 1..0=3
amominu.w rd rs1 rs2 16..10=6 9..7=2 6..2=0x0A 1..0=3
amomaxu.w rd rs1 rs2 16..10=7 9..7=2 6..2=0x0A 1..0=3
amoadd.d rd rs1 rs2 16..10=0 9..7=3 6..2=0x0A 1..0=3
amoswap.d rd rs1 rs2 16..10=1 9..7=3 6..2=0x0A 1..0=3
amoand.d rd rs1 rs2 16..10=2 9..7=3 6..2=0x0A 1..0=3
amoor.d rd rs1 rs2 16..10=3 9..7=3 6..2=0x0A 1..0=3
amomin.d rd rs1 rs2 16..10=4 9..7=3 6..2=0x0A 1..0=3
amomax.d rd rs1 rs2 16..10=5 9..7=3 6..2=0x0A 1..0=3
amominu.d rd rs1 rs2 16..10=6 9..7=3 6..2=0x0A 1..0=3
amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3
fence.i rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3
fence rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3
syscall 31..27=0 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1D 1..0=3
break 31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x1D 1..0=3
rdcycle rd 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3
rdtime rd 26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3
rdinstret rd 26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3
# vector fence instructions
fence.l.v rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3
fence.g.v rd rs1 imm12 9..7=5 6..2=0x0B 1..0=3
fence.l.cv rd rs1 imm12 9..7=6 6..2=0x0B 1..0=3
fence.g.cv rd rs1 imm12 9..7=7 6..2=0x0B 1..0=3
# vector scalar instructions
stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3
utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3
movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3
movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3
fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3
fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3
ei rd 26..22=0 21..17=0 16..7=0 6..2=0x1E 1..0=3
di rd 26..22=0 21..17=0 16..7=1 6..2=0x1E 1..0=3
mfpcr rd 26..22=0 rs2 16..7=2 6..2=0x1E 1..0=3
mtpcr 31..27=0 rs1 rs2 16..7=3 6..2=0x1E 1..0=3
eret 31..27=0 26..22=0 21..17=0 16..7=4 6..2=0x1E 1..0=3
cflush 31..27=0 26..22=0 21..17=0 16..7=5 6..2=0x1E 1..0=3
venqcmd 31..27=0 rs1 rs2 16..7=0x200 6..2=0x1E 1..0=3
venqimm1 31..27=0 rs1 rs2 16..7=0x201 6..2=0x1E 1..0=3
venqimm2 31..27=0 rs1 rs2 16..7=0x202 6..2=0x1E 1..0=3
venqcnt 31..27=0 rs1 rs2 16..7=0x203 6..2=0x1E 1..0=3
vwaitxcpt 31..27=0 26..22=0 21..17=0 16..7=0x300 6..2=0x1E 1..0=3
vwaitkill 31..27=0 26..22=0 21..17=0 16..7=0x301 6..2=0x1E 1..0=3
# 0x7C-0x7F are reserved for >32b instructions
fadd.s rd rs1 rs2 16..12=0 rm 8..7=0 6..2=0x14 1..0=3
fsub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..2=0x14 1..0=3
fmul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..2=0x14 1..0=3
fdiv.s rd rs1 rs2 16..12=3 rm 8..7=0 6..2=0x14 1..0=3
fsqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..2=0x14 1..0=3
fsgnj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..2=0x14 1..0=3
fsgnjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..2=0x14 1..0=3
fsgnjx.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..2=0x14 1..0=3
fadd.d rd rs1 rs2 16..12=0x0 rm 8..7=1 6..2=0x14 1..0=3
fsub.d rd rs1 rs2 16..12=0x1 rm 8..7=1 6..2=0x14 1..0=3
fmul.d rd rs1 rs2 16..12=0x2 rm 8..7=1 6..2=0x14 1..0=3
fdiv.d rd rs1 rs2 16..12=0x3 rm 8..7=1 6..2=0x14 1..0=3
fsqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=1 6..2=0x14 1..0=3
fsgnj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=1 6..2=0x14 1..0=3
fsgnjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=1 6..2=0x14 1..0=3
fsgnjx.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=1 6..2=0x14 1..0=3
fcvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..2=0x14 1..0=3
fcvt.lu.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..2=0x14 1..0=3
fcvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..2=0x14 1..0=3
fcvt.wu.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..2=0x14 1..0=3
fcvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=1 6..2=0x14 1..0=3
fcvt.lu.d rd rs1 21..17=0 16..12=0x9 rm 8..7=1 6..2=0x14 1..0=3
fcvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=1 6..2=0x14 1..0=3
fcvt.wu.d rd rs1 21..17=0 16..12=0xB rm 8..7=1 6..2=0x14 1..0=3
fcvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..2=0x14 1..0=3
fcvt.s.lu rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..2=0x14 1..0=3
fcvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..2=0x14 1..0=3
fcvt.s.wu rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..2=0x14 1..0=3
fcvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=1 6..2=0x14 1..0=3
fcvt.d.lu rd rs1 21..17=0 16..12=0xD rm 8..7=1 6..2=0x14 1..0=3
fcvt.d.w rd rs1 21..17=0 16..12=0xE rm 8..7=1 6..2=0x14 1..0=3
fcvt.d.wu rd rs1 21..17=0 16..12=0xF rm 8..7=1 6..2=0x14 1..0=3
fcvt.s.d rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3
fcvt.d.s rd rs1 21..17=0 16..14=0x4 13..12=0 rm 8..7=1 6..2=0x14 1..0=3
feq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3
flt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3
fle.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..2=0x14 1..0=3
feq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=1 6..2=0x14 1..0=3
flt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=1 6..2=0x14 1..0=3
fle.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=1 6..2=0x14 1..0=3
fmin.s rd rs1 rs2 16..12=0x18 11..9=0 8..7=0 6..2=0x14 1..0=3
fmax.s rd rs1 rs2 16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3
fmin.d rd rs1 rs2 16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3
fmax.d rd rs1 rs2 16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3
mftx.s rd 26..22=0 rs2 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3
mftx.d rd 26..22=0 rs2 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3
mffsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3
mxtf.s rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3
mxtf.d rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3
mtfsr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3
flw rd rs1 imm12 9..7=2 6..2=0x01 1..0=3
fld rd rs1 imm12 9..7=3 6..2=0x01 1..0=3
fsw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x09 1..0=3
fsd imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x09 1..0=3
fmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x10 1..0=3
fmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x11 1..0=3
fnmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x12 1..0=3
fnmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x13 1..0=3
fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3
fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3
fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3
fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3
# vector load mem instructions
# 3=d
# 2=seg 2=w
# 1=st 1=seg 1=f 1=s 1=h
# 0=u 0=etc 0=x 0=u 0=b
# ----------------------------------------------------------------------------
# mem padding type seg x/f u/s width opcode
# unit stride | | | | | | | |
# xloads | | | | | | | |
vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# mem padding type seg x/f u/s width opcode
# stride | | | | | | | |
# xloads | | | | | | | |
vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# mem padding type seg x/f u/s width opcode
# segment | | | | | | | |
# xloads | | | | | | | |
vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# seg x/f u/s width opcode
# stride segment | | | | |
# xloads | | | | |
vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# vector store mem instructions
# mem padding type seg x/f u/s width opcode
# unit stride | | | | | | | |
# xstores | | | | | | | |
vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# mem padding type seg x/f u/s width opcode
# stride | | | | | | | |
# xstores | | | | | | | |
vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# mem padding type seg x/f u/s width opcode
# segment | | | | | | | |
# xstores | | | | | | | |
vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# seg x/f u/s width opcode
# stride segment | | | | |
# xstores | | | | |
vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# other vector register instructions
vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3
vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3
vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3
vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3
vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3
vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3
vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3
vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3
# other vector immediate instructions
vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3
vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3
vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3
vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3
# compressed instructions
c.li cimm6 crd 4..0=0
c.addi cimm6 crd 4..0=1
c.addiw cimm6 crd 4..0=29
c.ldsp cimm6 crd 4..0=4
c.lwsp cimm6 crd 4..0=5
c.sdsp cimm6 crd 4..0=6
c.swsp cimm6 crd 4..0=8
c.lw0 15=0 crs1 crd 4..0=18
c.ld0 15=1 crs1 crd 4..0=18
c.add 15=0 crs1 crd 4..0=26
c.sub 15=1 crs1 crd 4..0=26
c.move 15=0 crs1 crd 4..0=2
c.j 15=1 cimm10 4..0=2
c.ld crds crs1s cimm5 4..0=9
c.lw crds crs1s cimm5 4..0=10
c.sd crs2s crs1s cimm5 4..0=12
c.sw crs2s crs1s cimm5 4..0=13
c.beq crs2s crs1s cimm5 4..0=16
c.bne crs2s crs1s cimm5 4..0=17
c.flw crds crs1s cimm5 4..0=20
c.fld crds crs1s cimm5 4..0=21
c.fsw crs2s crs1s cimm5 4..0=22
c.fsd crs2s crs1s cimm5 4..0=24
c.slli crds 12..10=0 cimm5 4..0=25
c.slli32 crds 12..10=1 cimm5 4..0=25
c.srli crds 12..10=2 cimm5 4..0=25
c.srli32 crds 12..10=3 cimm5 4..0=25
c.srai crds 12..10=4 cimm5 4..0=25
c.srai32 crds 12..10=5 cimm5 4..0=25
c.slliw crds 12..10=6 cimm5 4..0=25
c.add3 crds crs1s 9..8=0 crs2bs 4..0=28
c.sub3 crds crs1s 9..8=1 crs2bs 4..0=28
c.or3 crds crs1s 9..8=2 crs2bs 4..0=28
c.and3 crds crs1s 9..8=3 crs2bs 4..0=28
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