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# format of a line in this file:
# <instruction name> <opcode> <args>
#
# <opcode> is given by specifying one or more range/value pairs:
# highbit..lowbit=value (e.g. 6..2=0x45 9..7=0x0)
#
# <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw

unimp   31..0=0

j       imm25 6..2=0x19 1..0=3
jal     imm25 6..2=0x1B 1..0=3

jalr.c  rd rs1 imm12 9..7=0 6..2=0x1A 1..0=3
jalr.r  rd rs1 imm12 9..7=1 6..2=0x1A 1..0=3
jalr.j  rd rs1 imm12 9..7=2 6..2=0x1A 1..0=3

beq     imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3
bne     imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3
blt     imm12hi rs1 rs2 imm12lo 9..7=4 6..2=0x18 1..0=3
bge     imm12hi rs1 rs2 imm12lo 9..7=5 6..2=0x18 1..0=3
bltu    imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3
bgeu    imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3

lui     rd imm20 6..2=0x0D 1..0=3

addi    rd rs1 imm12               9..7=0 6..2=0x04 1..0=3
slli    rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3
slti    rd rs1 imm12               9..7=2 6..2=0x04 1..0=3
sltiu   rd rs1 imm12               9..7=3 6..2=0x04 1..0=3
xori    rd rs1 imm12               9..7=4 6..2=0x04 1..0=3
srli    rd rs1 21..17=0 16=0 shamt 9..7=5 6..2=0x04 1..0=3
srai    rd rs1 21..17=0 16=1 shamt 9..7=5 6..2=0x04 1..0=3
ori     rd rs1 imm12               9..7=6 6..2=0x04 1..0=3
andi    rd rs1 imm12               9..7=7 6..2=0x04 1..0=3

add     rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0C 1..0=3
sub     rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0C 1..0=3
sll     rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0C 1..0=3
slt     rd rs1 rs2 16=0 15..10=0 9..7=2 6..2=0x0C 1..0=3
sltu    rd rs1 rs2 16=0 15..10=0 9..7=3 6..2=0x0C 1..0=3
xor     rd rs1 rs2 16=0 15..10=0 9..7=4 6..2=0x0C 1..0=3
srl     rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0C 1..0=3
sra     rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0C 1..0=3
or      rd rs1 rs2 16=0 15..10=0 9..7=6 6..2=0x0C 1..0=3
and     rd rs1 rs2 16=0 15..10=0 9..7=7 6..2=0x0C 1..0=3

mul     rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0C 1..0=3
mulh    rd rs1 rs2 16=0 15..10=1 9..7=1 6..2=0x0C 1..0=3
mulhsu  rd rs1 rs2 16=0 15..10=1 9..7=2 6..2=0x0C 1..0=3
mulhu   rd rs1 rs2 16=0 15..10=1 9..7=3 6..2=0x0C 1..0=3
div     rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0C 1..0=3
divu    rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0C 1..0=3
rem     rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0C 1..0=3
remu    rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0C 1..0=3

addiw   rd rs1 imm12                     9..7=0 6..2=0x06 1..0=3
slliw   rd rs1 21..17=0 16=0 15=0 shamtw 9..7=1 6..2=0x06 1..0=3
srliw   rd rs1 21..17=0 16=0 15=0 shamtw 9..7=5 6..2=0x06 1..0=3
sraiw   rd rs1 21..17=0 16=1 15=0 shamtw 9..7=5 6..2=0x06 1..0=3

addw    rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0E 1..0=3
subw    rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0E 1..0=3
sllw    rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0E 1..0=3
srlw    rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0E 1..0=3
sraw    rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0E 1..0=3

mulw    rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0E 1..0=3
divw    rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0E 1..0=3
divuw   rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0E 1..0=3
remw    rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0E 1..0=3
remuw   rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0E 1..0=3

l.b     rd rs1       imm12 9..7=0 6..2=0x00 1..0=3
l.h     rd rs1       imm12 9..7=1 6..2=0x00 1..0=3
l.w     rd rs1       imm12 9..7=2 6..2=0x00 1..0=3
l.d     rd rs1       imm12 9..7=3 6..2=0x00 1..0=3
l.bu    rd rs1       imm12 9..7=4 6..2=0x00 1..0=3
l.hu    rd rs1       imm12 9..7=5 6..2=0x00 1..0=3
l.wu    rd rs1       imm12 9..7=6 6..2=0x00 1..0=3
synci   31..27=0 rs1 imm12 9..7=7 6..2=0x00 1..0=3

# NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c
# and elfxx-mips.c to detect them.  this is a hack to handle the split immed.
# just open up those files and search for MATCH_S_W; should be obvious.
s.b     imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3
s.h     imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3
s.w     imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3
s.d     imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x08 1..0=3

amoadd.w    rd rs1 rs2 16..10=0 9..7=2 6..2=0x10 1..0=3
amoswap.w   rd rs1 rs2 16..10=1 9..7=2 6..2=0x10 1..0=3
amoand.w    rd rs1 rs2 16..10=2 9..7=2 6..2=0x10 1..0=3
amoor.w     rd rs1 rs2 16..10=3 9..7=2 6..2=0x10 1..0=3
amomin.w    rd rs1 rs2 16..10=4 9..7=2 6..2=0x10 1..0=3
amomax.w    rd rs1 rs2 16..10=5 9..7=2 6..2=0x10 1..0=3
amominu.w   rd rs1 rs2 16..10=6 9..7=2 6..2=0x10 1..0=3
amomaxu.w   rd rs1 rs2 16..10=7 9..7=2 6..2=0x10 1..0=3
                                        
amoadd.d     rd rs1 rs2 16..10=0 9..7=3 6..2=0x10 1..0=3
amoswap.d    rd rs1 rs2 16..10=1 9..7=3 6..2=0x10 1..0=3
amoand.d     rd rs1 rs2 16..10=2 9..7=3 6..2=0x10 1..0=3
amoor.d      rd rs1 rs2 16..10=3 9..7=3 6..2=0x10 1..0=3
amomin.d     rd rs1 rs2 16..10=4 9..7=3 6..2=0x10 1..0=3
amomax.d     rd rs1 rs2 16..10=5 9..7=3 6..2=0x10 1..0=3
amominu.d    rd rs1 rs2 16..10=6 9..7=3 6..2=0x10 1..0=3
amomaxu.d    rd rs1 rs2 16..10=7 9..7=3 6..2=0x10 1..0=3

rdnpc   rd       26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x05 1..0=3
mfcr    rd       26..22=0 rs2      16..10=0 9..7=1 6..2=0x05 1..0=3
mtcr    31..27=0 rs1      rs2      16..10=1 9..7=1 6..2=0x05 1..0=3
sync    31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x05 1..0=3
syscall 31..27=0 26..22=0        imm12      9..7=3 6..2=0x05 1..0=3

ei      rd       26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1F 1..0=3
di      rd       26..22=0 21..17=0 16..10=1 9..7=0 6..2=0x1F 1..0=3
mfpcr   rd       26..22=0 rs2      16..10=0 9..7=1 6..2=0x1F 1..0=3
mtpcr   31..27=0 rs1      rs2      16..10=1 9..7=1 6..2=0x1F 1..0=3
eret    31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1F 1..0=3

# 0x7C-0x7F are reserved for >32b instructions

fadd.s      rd rs1 rs2      16..12=0    rm      8..7=0 6..2=0x14 1..0=3
fsub.s      rd rs1 rs2      16..12=1    rm      8..7=0 6..2=0x14 1..0=3
fmul.s      rd rs1 rs2      16..12=2    rm      8..7=0 6..2=0x14 1..0=3
fdiv.s      rd rs1 rs2      16..12=3    rm      8..7=0 6..2=0x14 1..0=3
fsqrt.s     rd rs1 21..17=0 16..12=4    rm      8..7=0 6..2=0x14 1..0=3
fsinj.s     rd rs1 rs2      16..12=5    11..9=0 8..7=0 6..2=0x14 1..0=3
fsinjn.s    rd rs1 rs2      16..12=6    11..9=0 8..7=0 6..2=0x14 1..0=3
fsmul.s     rd rs1 rs2      16..12=7    11..9=0 8..7=0 6..2=0x14 1..0=3

fadd.d      rd rs1 rs2      16..12=0x0  rm      8..7=1 6..2=0x14 1..0=3
fsub.d      rd rs1 rs2      16..12=0x1  rm      8..7=1 6..2=0x14 1..0=3
fmul.d      rd rs1 rs2      16..12=0x2  rm      8..7=1 6..2=0x14 1..0=3
fdiv.d      rd rs1 rs2      16..12=0x3  rm      8..7=1 6..2=0x14 1..0=3
fsqrt.d     rd rs1 21..17=0 16..12=0x4  rm      8..7=1 6..2=0x14 1..0=3
fsinj.d     rd rs1 rs2      16..12=0x5  11..9=0 8..7=1 6..2=0x14 1..0=3
fsinjn.d    rd rs1 rs2      16..12=0x6  11..9=0 8..7=1 6..2=0x14 1..0=3
fsmul.d     rd rs1 rs2      16..12=0x7  11..9=0 8..7=1 6..2=0x14 1..0=3

fcvt.l.s    rd rs1 21..17=0 16..12=0x8  rm      8..7=0 6..2=0x14 1..0=3
fcvtu.l.s   rd rs1 21..17=0 16..12=0x9  rm      8..7=0 6..2=0x14 1..0=3
fcvt.w.s    rd rs1 21..17=0 16..12=0xA  rm      8..7=0 6..2=0x14 1..0=3
fcvtu.w.s   rd rs1 21..17=0 16..12=0xB  rm      8..7=0 6..2=0x14 1..0=3

fcvt.l.d    rd rs1 21..17=0 16..12=0x8  rm      8..7=1 6..2=0x14 1..0=3
fcvtu.l.d   rd rs1 21..17=0 16..12=0x9  rm      8..7=1 6..2=0x14 1..0=3
fcvt.w.d    rd rs1 21..17=0 16..12=0xA  rm      8..7=1 6..2=0x14 1..0=3
fcvtu.w.d   rd rs1 21..17=0 16..12=0xB  rm      8..7=1 6..2=0x14 1..0=3

fcvt.s.l    rd rs1 21..17=0 16..12=0xC  rm      8..7=0 6..2=0x14 1..0=3
fcvtu.s.l   rd rs1 21..17=0 16..12=0xD  rm      8..7=0 6..2=0x14 1..0=3
fcvt.s.w    rd rs1 21..17=0 16..12=0xE  rm      8..7=0 6..2=0x14 1..0=3
fcvtu.s.w   rd rs1 21..17=0 16..12=0xF  rm      8..7=0 6..2=0x14 1..0=3

fcvt.d.l    rd rs1 21..17=0 16..12=0xC  rm      8..7=1 6..2=0x14 1..0=3
fcvtu.d.l   rd rs1 21..17=0 16..12=0xD  rm      8..7=1 6..2=0x14 1..0=3
fcvt.d.w    rd rs1 21..17=0 16..12=0xE  11..9=0 8..7=1 6..2=0x14 1..0=3
fcvtu.d.w   rd rs1 21..17=0 16..12=0xF  11..9=0 8..7=1 6..2=0x14 1..0=3

fcvt.s.d    rd rs1 21..17=0 16..14=0x4 13..12=1 rm      8..7=0 6..2=0x14 1..0=3
fcvt.d.s    rd rs1 21..17=0 16..14=0x4 13..12=0 11..9=0 8..7=1 6..2=0x14 1..0=3

fc.eq.s     rd rs1 rs2      16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3
fc.lt.s     rd rs1 rs2      16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3
fc.le.s     rd rs1 rs2      16..12=0x17 11..9=0 8..7=0 6..2=0x14 1..0=3

fc.eq.d     rd rs1 rs2      16..12=0x15 11..9=0 8..7=1 6..2=0x14 1..0=3
fc.lt.d     rd rs1 rs2      16..12=0x16 11..9=0 8..7=1 6..2=0x14 1..0=3
fc.le.d     rd rs1 rs2      16..12=0x17 11..9=0 8..7=1 6..2=0x14 1..0=3

mff.s       rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=0 6..2=0x14 1..0=3
mff.d       rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=1 6..2=0x14 1..0=3
mffl.d      rd 26..22=0 rs2 16..12=0x19 11..9=2 8..7=1 6..2=0x14 1..0=3
mffh.d      rd 26..22=0 rs2 16..12=0x1A 11..9=2 8..7=1 6..2=0x14 1..0=3
mtf.s       rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=0 6..2=0x14 1..0=3
mtf.d       rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=1 6..2=0x14 1..0=3
mtflh.d     rd rs1 rs2      16..12=0x1C 11..9=3 8..7=1 6..2=0x14 1..0=3

lf.w        rd rs1 imm12 9..7=2 6..2=0x01 1..0=3
lf.d        rd rs1 imm12 9..7=3 6..2=0x01 1..0=3

sf.w        imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x09 1..0=3
sf.d        imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x09 1..0=3

fmadd.s     rd rs1 rs2 rs3 rm 8..7=0 6..2=0x10 1..0=3
fmsub.s     rd rs1 rs2 rs3 rm 8..7=0 6..2=0x11 1..0=3
fnmsub.s    rd rs1 rs2 rs3 rm 8..7=0 6..2=0x12 1..0=3
fnmadd.s    rd rs1 rs2 rs3 rm 8..7=0 6..2=0x13 1..0=3

fmadd.d     rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3
fmsub.d     rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3
fnmsub.d    rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3
fnmadd.d    rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3