riscv-opcodes - RISC-V opcodes

	Commit message (Expand)	Author	Age
*	Move stats register	Stephen Twigg	2014-04-03
*	Add rdcycleh etc. for RV32	Andrew Waterman	2014-03-18
*	Fix syntax error in generated opcodes	Andrew Waterman	2014-03-11
*	New FP encoding	Andrew Waterman	2014-03-11
*	Add fclass.{s\|d} instructions	Andrew Waterman	2014-03-06
*	Renumber uarch CSRs into custom CSR space	Andrew Waterman	2014-02-14
*	Reserve 16 uarch-specific read-only userspace counters	Andrew Waterman	2014-02-06
*	Add DECLARE_CAUSE macro	Andrew Waterman	2014-01-21
*	Auto-generate exception cause numbers	Andrew Waterman	2014-01-21
*	New RDCYCLE encoding	Andrew Waterman	2013-12-09
*	New privileged ISA	Andrew Waterman	2013-11-25
*	add missing imm for stores	Yunsup Lee	2013-11-22
*	changes to the instr-table	Yunsup Lee	2013-10-29
*	revamp hwacha-v3 opcodes	Yunsup Lee	2013-10-10
*	Fix funct field in tables.	Andrew Waterman	2013-09-21
*	Update ISA encoding	Andrew Waterman	2013-09-21
*	hwacha v3: inst format follows the new rocket accelerator extensions	Yunsup Lee	2013-08-07
*	Rename MTFSR/MFFSR to FSSR/FRSR	Andrew Waterman	2013-08-06
*	HW ignores upper bits of fence, but SW supplies 0	Andrew Waterman	2013-07-31
*	tweaks	Yunsup Lee	2013-07-26
*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
*	Refactor parse-opcodes	Andrew Waterman	2013-07-25
*	add auipc, lr, sc	Andrew Waterman	2013-04-17
*	temporary undoing of renaming	Andrew Waterman	2011-06-19
*	Renamed packages	Andrew Waterman	2011-06-19
*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19
*	[sim, opcodes] made sim more decoupled from opcodes	Andrew Waterman	2011-06-10
*	[sim,opcodes] improved sim build and run performance	Andrew Waterman	2011-05-29
*	[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)	Yunsup Lee	2011-05-18
*	[libs,opcodes,pk,sim,xcc] add mov,fmov, shuffle vec insts	Yunsup Lee	2011-05-15
*	[xcc,sim,opcodes] added c.addiw	Andrew Waterman	2011-04-24
*	[xcc,sim,opcodes] added more RVC instructions	Andrew Waterman	2011-04-24
*	[xcc,sim] rvc loads and stores	Andrew Waterman	2011-04-12
*	[xcc,sim,opcodes] more rvc instructions and bug fixes	Andrew Waterman	2011-04-11
*	[xcc, sim] added rvc insn c.li; misc fixes	Andrew Waterman	2011-04-09
*	[xcc,pk,sim,opcodes] added first RVC instruction	Andrew Waterman	2011-04-09
*	[pk,sim] fixed parse-opcodes bug	Andrew Waterman	2011-04-07
*	[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...	Yunsup Lee	2011-04-05
*	[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)	Yunsup Lee	2011-04-04
*	[opcodes,pk,sim,xcc] add vector mem instructions	Yunsup Lee	2011-04-04
*	[opcodes] fixed up instruction table	Andrew Waterman	2011-03-25
*	[xcc,pk,opcodes,sim] updated encoding/insn names	Andrew Waterman	2011-03-25
*	[opcodes] fixed verilog generation for shifts	Andrew Waterman	2011-01-31
*	[opcodes,pk,sim,xcc] great renumbering of 2011, part deux	Andrew Waterman	2011-01-25
*	[sim, pk, xcc, opcodes] great instruction renaming of 2011	Andrew Waterman	2011-01-20
*	[opcodes,pk,sim,xcc] flip fields to favor little endian	Yunsup Lee	2011-01-03
*	[opcodes, pk, sim, xcc] Tweaked FP encoding	Andrew Waterman	2010-11-21
*	[opcodes] generate latex and verilog correctly	Andrew Waterman	2010-11-21
*	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	2010-11-21
*	[opcodes, pk, sim, xcc] made jumps shorter and PC-relative	Andrew Waterman	2010-11-21