summaryrefslogtreecommitdiff
path: root/parse-opcodes
Commit message (Expand)AuthorAge
* Use BitPat instead of Bits for Chisel3Gravatar Andrew Waterman2015-09-08
* update to latest RVC proposalGravatar Andrew Waterman2015-09-08
* Fix DECLARE_CAUSE macrosGravatar Andrew Waterman2015-07-28
* New machine-mode timer facilityGravatar Andrew Waterman2015-07-05
* Update to privileged architecture version 1.7Gravatar Andrew Waterman2015-05-09
* RVC draftGravatar Andrew Waterman2015-03-30
* Merge [shm]call into ecall, [shm]ret into eretGravatar Andrew Waterman2015-03-17
* Update to new privileged specGravatar Andrew Waterman2015-03-12
* Move stats registerGravatar Stephen Twigg2014-04-03
* Add rdcycleh etc. for RV32Gravatar Andrew Waterman2014-03-18
* Fix syntax error in generated opcodesGravatar Andrew Waterman2014-03-11
* New FP encodingGravatar Andrew Waterman2014-03-11
* Add fclass.{s|d} instructionsGravatar Andrew Waterman2014-03-06
* Renumber uarch CSRs into custom CSR spaceGravatar Andrew Waterman2014-02-14
* Reserve 16 uarch-specific read-only userspace countersGravatar Andrew Waterman2014-02-06
* Add DECLARE_CAUSE macroGravatar Andrew Waterman2014-01-21
* Auto-generate exception cause numbersGravatar Andrew Waterman2014-01-21
* New RDCYCLE encodingGravatar Andrew Waterman2013-12-09
* New privileged ISAGravatar Andrew Waterman2013-11-25
* add missing imm for storesGravatar Yunsup Lee2013-11-22
* changes to the instr-tableGravatar Yunsup Lee2013-10-29
* revamp hwacha-v3 opcodesGravatar Yunsup Lee2013-10-10
* Fix funct field in tables.Gravatar Andrew Waterman2013-09-21
* Update ISA encodingGravatar Andrew Waterman2013-09-21
* hwacha v3: inst format follows the new rocket accelerator extensionsGravatar Yunsup Lee2013-08-07
* Rename MTFSR/MFFSR to FSSR/FRSRGravatar Andrew Waterman2013-08-06
* HW ignores upper bits of fence, but SW supplies 0Gravatar Andrew Waterman2013-07-31
* tweaksGravatar Yunsup Lee2013-07-26
* Factor out Hwacha/RVC and rename MFTX/MXTF to FMVGravatar Andrew Waterman2013-07-26
* Refactor parse-opcodesGravatar Andrew Waterman2013-07-25
* add auipc, lr, scGravatar Andrew Waterman2013-04-17
* temporary undoing of renamingGravatar Andrew Waterman2011-06-19
* Renamed packagesGravatar Andrew Waterman2011-06-19
* [riscv-isa-run] code cleanup; added READMEGravatar Andrew Waterman2011-06-19
* [sim, opcodes] made sim more decoupled from opcodesGravatar Andrew Waterman2011-06-10
* [sim,opcodes] improved sim build and run performanceGravatar Andrew Waterman2011-05-29
* [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Gravatar Yunsup Lee2011-05-18
* [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsGravatar Yunsup Lee2011-05-15
* [xcc,sim,opcodes] added c.addiwGravatar Andrew Waterman2011-04-24
* [xcc,sim,opcodes] added more RVC instructionsGravatar Andrew Waterman2011-04-24
* [xcc,sim] rvc loads and storesGravatar Andrew Waterman2011-04-12
* [xcc,sim,opcodes] more rvc instructions and bug fixesGravatar Andrew Waterman2011-04-11
* [xcc, sim] added rvc insn c.li; misc fixesGravatar Andrew Waterman2011-04-09
* [xcc,pk,sim,opcodes] added first RVC instructionGravatar Andrew Waterman2011-04-09
* [pk,sim] fixed parse-opcodes bugGravatar Andrew Waterman2011-04-07
* [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Gravatar Yunsup Lee2011-04-05
* [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Gravatar Yunsup Lee2011-04-04
* [opcodes,pk,sim,xcc] add vector mem instructionsGravatar Yunsup Lee2011-04-04
* [opcodes] fixed up instruction tableGravatar Andrew Waterman2011-03-25
* [xcc,pk,opcodes,sim] updated encoding/insn namesGravatar Andrew Waterman2011-03-25
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-24 05:02:29 +0000