| Commit message (Expand) | Author | Age |
* | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 2010-09-20 |
* | [xcc, sim] replaced ble/bleu with bge/bgeu | Andrew Waterman | 2010-09-13 |
* | [opcodes] fixed tex table for ish,ishw types | Yunsup Lee | 2010-09-12 |
* | [sim] renamed sllv to sll (same for other shifts) | Andrew Waterman | 2010-09-12 |
* | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 2010-09-12 |
* | [xcc, sim] branches now are next-PC-based, not PC-based | Andrew Waterman | 2010-09-12 |
* | [sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit | Andrew Waterman | 2010-09-10 |
* | [opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit) | Yunsup Lee | 2010-09-10 |
* | [opcodes] latex table generation added, new opcode mapping | Yunsup Lee | 2010-09-10 |