Commit message (Collapse) | Author | Age | |
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* | Fix funct field in tables. | 2013-09-21 | |
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* | Update ISA encoding | 2013-09-21 | |
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* | Rename MTFSR/MFFSR to FSSR/FRSR | 2013-08-06 | |
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* | HW ignores upper bits of fence, but SW supplies 0 | 2013-07-31 | |
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* | Swap J and JALR encodings | 2013-07-31 | |
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* | tweaks | 2013-07-26 | |
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* | Factor out Hwacha/RVC and rename MFTX/MXTF to FMV | 2013-07-26 | |
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* | Refactor parse-opcodes | 2013-07-25 | |
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* | add auipc, lr, sc | 2013-04-17 | |
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* | change vector fence names/encoding | 2012-03-18 | |
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* | opcodes cleanup | 2012-03-13 | |
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* | temporary undoing of renaming | 2011-06-19 | |
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* | Renamed packages | 2011-06-19 | |
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* | [opcodes,pk,sim,xcc] resolve a conflict | 2011-05-15 | |
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* | [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts | 2011-05-15 | |
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* | tweaked encoding of rdcycle & cousins | 2011-05-13 | |
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* | [opcodes,pk,sim,xcc] fix utidx - add rd | 2011-04-06 | |
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* | [opcodes,pk,sim,xcc] add stop,utidx instructions | 2011-04-04 | |
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* | [opcodes,pk,sim,xcc] add fence instructions for vector unit | 2011-04-04 | |
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* | [opcodes] fixed up instruction table | 2011-03-25 | |
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* | [xcc,pk,opcodes,sim] updated encoding/insn names | 2011-03-25 | |
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* | [xcc,opcodes,pk,sim] krste's re-renaming spree | 2011-02-15 | |
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* | [xcc,sim,opcodes] removed mtflh/mffl/mffh | 2011-02-15 | |
| | | | | in rv32 these will be replaced with loads and stores. | ||
* | [sim,xcc,opcodes] added back mtflh.d | 2011-02-02 | |
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* | [opcodes,pk,sim,xcc] synci now bombs whole icache | 2011-02-02 | |
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* | [xcc,opcodes,pk,sim] cleanup to FP ISA | 2011-02-01 | |
| | | | | | | | - Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64 | ||
* | [sim,opcodes] add mulhsu instruction | 2011-01-25 | |
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* | [opcodes,pk,sim,xcc] great renumbering of 2011, part deux | 2011-01-25 | |
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* | [sim, pk, xcc, opcodes] great instruction renaming of 2011 | 2011-01-20 | |
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* | [opcodes, sim, xcc] made *w insns illegal in RV32 | 2011-01-18 | |
| | | | | now generic variants behave differently in RV32 and RV64. | ||
* | [opcodes, pk, sim, xcc] removed nor, normalized macros to addi | 2011-01-17 | |
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* | [opcodes,pk,sim,xcc] flip fields to favor little endian | 2011-01-03 | |
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* | [opcodes, pk, sim, xcc] Tweaked FP encoding | 2010-11-21 | |
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* | [opcodes] generate latex and verilog correctly | 2010-11-21 | |
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* | [xcc, sim, pk, opcodes] new instruction encoding! | 2010-11-21 | |
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* | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | 2010-11-21 | |
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* | [opcodes] add latex table for rm stuff | 2010-10-31 | |
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* | [sim,xcc,pk,opcodes] static rounding modes for FP insns | 2010-10-25 | |
| | | | | | | Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.) | ||
* | [opcodes] changed formatting of optab section headers | 2010-10-20 | |
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* | [pk, sim] added FPU emulation support to proxy kernel | 2010-10-15 | |
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* | [xcc] modified opcodes for better FP decode mapping | 2010-10-07 | |
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* | [opcodes] added code field back to syscall/break | 2010-10-05 | |
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* | [opcodes] updated parse-opcodes for latex tables | 2010-10-05 | |
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* | [opcodes] update parse-opcodes | 2010-10-05 | |
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* | [xcc, sim] mff now uses rs2 for data | 2010-10-02 | |
| | | | | this is symmetric with fp stores, so we only need one decoding pipe | ||
* | [opcodes, sim, xcc] added mffl.d instruction | 2010-09-28 | |
| | | | | ...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu | ||
* | [xcc, sim] changed instruction format so imm12 subs for rs2 | 2010-09-20 | |
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* | [xcc, sim] replaced ble/bleu with bge/bgeu | 2010-09-13 | |
| | | | | This will simplify control logic (since every branch has a logical inverse) | ||
* | [opcodes] fixed tex table for ish,ishw types | 2010-09-12 | |
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* | [sim] renamed sllv to sll (same for other shifts) | 2010-09-12 | |
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