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* [opcodes,pk,sim,xcc] flip fields to favor little endianGravatar Yunsup Lee2011-01-03
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* [opcodes, pk, sim, xcc] Tweaked FP encodingGravatar Andrew Waterman2010-11-21
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* [opcodes] generate latex and verilog correctlyGravatar Andrew Waterman2010-11-21
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* [xcc, sim, pk, opcodes] new instruction encoding!Gravatar Andrew Waterman2010-11-21
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* [opcodes, pk, sim, xcc] made jumps shorter and PC-relativeGravatar Andrew Waterman2010-11-21
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* [opcodes] add latex table for rm stuffGravatar Yunsup Lee2010-10-31
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* [sim,xcc,pk,opcodes] static rounding modes for FP insnsGravatar Andrew Waterman2010-10-25
| | | | | | Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
* [opcodes] changed formatting of optab section headersGravatar Andrew Waterman2010-10-20
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* [pk, sim] added FPU emulation support to proxy kernelGravatar Andrew Waterman2010-10-15
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* [xcc] modified opcodes for better FP decode mappingGravatar Andrew Waterman2010-10-07
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* [opcodes] added code field back to syscall/breakGravatar Andrew Waterman2010-10-05
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* [opcodes] updated parse-opcodes for latex tablesGravatar Yunsup Lee2010-10-05
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* [opcodes] update parse-opcodesGravatar Yunsup Lee2010-10-05
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* [xcc, sim] mff now uses rs2 for dataGravatar Andrew Waterman2010-10-02
| | | | this is symmetric with fp stores, so we only need one decoding pipe
* [opcodes, sim, xcc] added mffl.d instructionGravatar Andrew Waterman2010-09-28
| | | | ...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
* [xcc, sim] changed instruction format so imm12 subs for rs2Gravatar Andrew Waterman2010-09-20
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* [xcc, sim] replaced ble/bleu with bge/bgeuGravatar Andrew Waterman2010-09-13
| | | | This will simplify control logic (since every branch has a logical inverse)
* [opcodes] fixed tex table for ish,ishw typesGravatar Yunsup Lee2010-09-12
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* [sim] renamed sllv to sll (same for other shifts)Gravatar Andrew Waterman2010-09-12
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* [xcc, sim] moved shamt field and renamed shiftsGravatar Andrew Waterman2010-09-12
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* [xcc, sim] branches now are next-PC-based, not PC-basedGravatar Andrew Waterman2010-09-12
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* [sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitGravatar Andrew Waterman2010-09-10
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* [opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Gravatar Yunsup Lee2010-09-10
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* [opcodes] latex table generation added, new opcode mappingGravatar Yunsup Lee2010-09-10
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