riscv-opcodes - RISC-V opcodes

	Commit message (Expand)	Author	Age
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*	[opcodes, pk, sim, xcc] made jumps shorter and PC-relative	Andrew Waterman	2010-11-21
*	[sim,xcc,pk,opcodes] static rounding modes for FP insns	Andrew Waterman	2010-10-25
*	[pk, sim] added FPU emulation support to proxy kernel	Andrew Waterman	2010-10-15
*	[xcc] modified opcodes for better FP decode mapping	Andrew Waterman	2010-10-07
*	[opcodes] updated parse-opcodes for latex tables	Yunsup Lee	2010-10-05
*	[opcodes] update parse-opcodes	Yunsup Lee	2010-10-05
*	[xcc, sim] mff now uses rs2 for data	Andrew Waterman	2010-10-02
*	[opcodes, sim, xcc] added mffl.d instruction	Andrew Waterman	2010-09-28
*	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	2010-09-20
*	[xcc, sim] replaced ble/bleu with bge/bgeu	Andrew Waterman	2010-09-13
*	[opcodes] fixed tex table for ish,ishw types	Yunsup Lee	2010-09-12
*	[opcodes] fixed verilog generation for ish,ishw types	Yunsup Lee	2010-09-12
*	[sim] renamed sllv to sll (same for other shifts)	Andrew Waterman	2010-09-12
*	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	2010-09-12
*	[xcc, sim] branches now are next-PC-based, not PC-based	Andrew Waterman	2010-09-12
*	add -verilog option	Yunsup Lee	2010-09-12