riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	New machine-mode timer facility	Andrew Waterman	2015-07-05
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*	Update to privileged architecture version 1.7	Andrew Waterman	2015-05-09
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*	Merge [shm]call into ecall, [shm]ret into eret	Andrew Waterman	2015-03-17
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*	Add hcall instruction	Andrew Waterman	2015-03-12
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*	Update to new privileged spec	Andrew Waterman	2015-03-12
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*	Move stats register	Stephen Twigg	2014-04-03
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*	Add rdcycleh etc. for RV32	Andrew Waterman	2014-03-18
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*	New FP encoding	Andrew Waterman	2014-03-11
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*	Add fclass.{s\|d} instructions	Andrew Waterman	2014-03-06
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*	Renumber uarch CSRs into custom CSR space	Andrew Waterman	2014-02-14
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*	Reserve 16 uarch-specific read-only userspace counters	Andrew Waterman	2014-02-06
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*	Auto-generate exception cause numbers	Andrew Waterman	2014-01-21
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*	swap JAL/JALR again	Andrew Waterman	2014-01-13
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*	New RDCYCLE encoding	Andrew Waterman	2013-12-09
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*	New privileged ISA	Andrew Waterman	2013-11-25
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*	fix slli/slliw encoding bug	Yunsup Lee	2013-11-21
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*	Update ISA encoding	Andrew Waterman	2013-09-21