diff options
author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-07-05 16:48:22 -0700 |
---|---|---|
committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-07-05 16:48:22 -0700 |
commit | 436835918e6801522f4b201b7304399e0714c6af (patch) | |
tree | a3ecda30c8bbe65c74b1c608036aafc3a7eaa528 /inst.chisel | |
parent | a5f329c88265a09674d47ef89db4ad2188c88636 (diff) |
New machine-mode timer facility
Diffstat (limited to 'inst.chisel')
-rw-r--r-- | inst.chisel | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/inst.chisel b/inst.chisel index 0c49d6c..f7bfd44 100644 --- a/inst.chisel +++ b/inst.chisel @@ -244,7 +244,6 @@ object CSRs { val sstatus = 0x100 val stvec = 0x101 val sie = 0x104 - val stimecmp = 0x121 val sscratch = 0x140 val sepc = 0x141 val sip = 0x144 @@ -283,6 +282,7 @@ object CSRs { val instrethw = 0x982 val stimeh = 0xd81 val stimehw = 0xa81 + val mtimecmph = 0x361 val mtimeh = 0x741 val all = { val res = collection.mutable.ArrayBuffer[Int]() @@ -312,7 +312,6 @@ object CSRs { res += sstatus res += stvec res += sie - res += stimecmp res += sscratch res += sepc res += sip @@ -355,6 +354,7 @@ object CSRs { res += instrethw res += stimeh res += stimehw + res += mtimecmph res += mtimeh res.toArray } |