diff options
Diffstat (limited to 'inst.chisel')
| -rw-r--r-- | inst.chisel | 114 |
1 files changed, 85 insertions, 29 deletions
diff --git a/inst.chisel b/inst.chisel index abda1c6..1b22a3e 100644 --- a/inst.chisel +++ b/inst.chisel @@ -1,4 +1,5 @@ - /* Automatically generated by parse-opcodes */ +/* Automatically generated by parse-opcodes */ +object Instructions { def JAL = Bits("b?????????????????????????1100111") def JALR = Bits("b?????????????????000?????1101111") def BEQ = Bits("b?????????????????000?????1100011") @@ -28,14 +29,6 @@ def SRA = Bits("b0100000??????????101?????0110011") def OR = Bits("b0000000??????????110?????0110011") def AND = Bits("b0000000??????????111?????0110011") - def MUL = Bits("b0000001??????????000?????0110011") - def MULH = Bits("b0000001??????????001?????0110011") - def MULHSU = Bits("b0000001??????????010?????0110011") - def MULHU = Bits("b0000001??????????011?????0110011") - def DIV = Bits("b0000001??????????100?????0110011") - def DIVU = Bits("b0000001??????????101?????0110011") - def REM = Bits("b0000001??????????110?????0110011") - def REMU = Bits("b0000001??????????111?????0110011") def ADDIW = Bits("b?????????????????000?????0011011") def SLLIW = Bits("b0000000??????????001?????0011011") def SRLIW = Bits("b0000000??????????101?????0011011") @@ -45,11 +38,6 @@ def SLLW = Bits("b0000000??????????001?????0111011") def SRLW = Bits("b0000000??????????101?????0111011") def SRAW = Bits("b0100000??????????101?????0111011") - def MULW = Bits("b0000001??????????000?????0111011") - def DIVW = Bits("b0000001??????????100?????0111011") - def DIVUW = Bits("b0000001??????????101?????0111011") - def REMW = Bits("b0000001??????????110?????0111011") - def REMUW = Bits("b0000001??????????111?????0111011") def LB = Bits("b?????????????????000?????0000011") def LH = Bits("b?????????????????001?????0000011") def LW = Bits("b?????????????????010?????0000011") @@ -61,6 +49,21 @@ def SH = Bits("b?????????????????001?????0100011") def SW = Bits("b?????????????????010?????0100011") def SD = Bits("b?????????????????011?????0100011") + def FENCE = Bits("b?????????????????000?????0001111") + def FENCE_I = Bits("b?????????????????001?????0001111") + def MUL = Bits("b0000001??????????000?????0110011") + def MULH = Bits("b0000001??????????001?????0110011") + def MULHSU = Bits("b0000001??????????010?????0110011") + def MULHU = Bits("b0000001??????????011?????0110011") + def DIV = Bits("b0000001??????????100?????0110011") + def DIVU = Bits("b0000001??????????101?????0110011") + def REM = Bits("b0000001??????????110?????0110011") + def REMU = Bits("b0000001??????????111?????0110011") + def MULW = Bits("b0000001??????????000?????0111011") + def DIVW = Bits("b0000001??????????100?????0111011") + def DIVUW = Bits("b0000001??????????101?????0111011") + def REMW = Bits("b0000001??????????110?????0111011") + def REMUW = Bits("b0000001??????????111?????0111011") def AMOADD_W = Bits("b00000????????????010?????0101111") def AMOXOR_W = Bits("b00100????????????010?????0101111") def AMOOR_W = Bits("b01000????????????010?????0101111") @@ -83,18 +86,15 @@ def AMOSWAP_D = Bits("b00001????????????011?????0101111") def LR_D = Bits("b00010??00000?????011?????0101111") def SC_D = Bits("b00011????????????011?????0101111") - def FENCE = Bits("b?????????????????000?????0001111") - def FENCE_I = Bits("b?????????????????001?????0001111") - def SYSCALL = Bits("b00000000000000000000000001110111") - def BREAK = Bits("b00000000000000000001000001110111") - def RDCYCLE = Bits("b00000000000000000100?????1110111") - def RDTIME = Bits("b00000010000000000100?????1110111") - def RDINSTRET = Bits("b00000100000000000100?????1110111") - def MTPCR = Bits("b0000000??????????000?????1110011") - def MFPCR = Bits("b000000000000?????001?????1110011") - def SETPCR = Bits("b?????????????????010?????1110011") - def CLEARPCR = Bits("b?????????????????011?????1110011") - def ERET = Bits("b00000000000000000100000001110011") + def SCALL = Bits("b00000000000000000000000001110011") + def SBREAK = Bits("b00000000000100000000000001110011") + def SRET = Bits("b10000000000000000000000001110011") + def CSRRW = Bits("b?????????????????001?????1110011") + def CSRRS = Bits("b?????????????????010?????1110011") + def CSRRC = Bits("b?????????????????011?????1110011") + def CSRRWI = Bits("b?????????????????101?????1110011") + def CSRRSI = Bits("b?????????????????110?????1110011") + def CSRRCI = Bits("b?????????????????111?????1110011") def FADD_S = Bits("b0000000??????????????????1010011") def FSUB_S = Bits("b0000100??????????????????1010011") def FMUL_S = Bits("b0001000??????????????????1010011") @@ -141,10 +141,8 @@ def FMAX_D = Bits("b1100101??????????000?????1010011") def FMV_X_S = Bits("b111000000000?????000?????1010011") def FMV_X_D = Bits("b111000100000?????000?????1010011") - def FRSR = Bits("b11101000000000000000?????1010011") def FMV_S_X = Bits("b111100000000?????000?????1010011") def FMV_D_X = Bits("b111100100000?????000?????1010011") - def FSSR = Bits("b111110000000?????000?????1010011") def FLW = Bits("b?????????????????010?????0000111") def FLD = Bits("b?????????????????011?????0000111") def FSW = Bits("b?????????????????010?????0100111") @@ -157,7 +155,6 @@ def FMSUB_D = Bits("b?????01??????????????????1000111") def FNMSUB_D = Bits("b?????01??????????????????1001011") def FNMADD_D = Bits("b?????01??????????????????1001111") - /* Automatically generated by parse-opcodes */ def CUSTOM0 = Bits("b?????????????????000?????0001011") def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011") def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011") @@ -182,3 +179,62 @@ def CUSTOM3_RD = Bits("b?????????????????100?????1111011") def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") +} +object CSRs { + val sup0 = 1280 + val fflags = 1 + val frm = 2 + val fcsr = 3 + val cycle = 4 + val time = 5 + val instret = 6 + val sup1 = 1281 + val evec = 1288 + val cause = 1289 + val status = 1290 + val hartid = 1291 + val impl = 1292 + val epc = 1282 + val send_ipi = 1294 + val clear_ipi = 1295 + val badvaddr = 1283 + val ptbr = 1284 + val stats = 1308 + val reset = 1309 + val tohost = 1310 + val asid = 1285 + val count = 1286 + val compare = 1287 + val fromhost = 1311 + val fatc = 1293 + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += sup0 + res += fflags + res += frm + res += fcsr + res += cycle + res += time + res += instret + res += sup1 + res += evec + res += cause + res += status + res += hartid + res += impl + res += epc + res += send_ipi + res += clear_ipi + res += badvaddr + res += ptbr + res += stats + res += reset + res += tohost + res += asid + res += count + res += compare + res += fromhost + res += fatc + res.toArray + } +} |