diff options
| -rw-r--r-- | instr-table.tex | 1752 | ||||
| -rw-r--r-- | opcodes | 363 | ||||
| -rwxr-xr-x | parse-opcodes | 642 | ||||
| -rwxr-xr-x | update-opcodes | 2 |
4 files changed, 2435 insertions, 324 deletions
diff --git a/instr-table.tex b/instr-table.tex new file mode 100644 index 0000000..5215aab --- /dev/null +++ b/instr-table.tex @@ -0,0 +1,1752 @@ + +\newpage + +\begin{table}[p] +\begin{small} +\begin{center} +\begin{tabular}{rcccccccccl} + & +\hspace*{0.6in} & +\hspace*{0.2in} & +\hspace*{0.5in} & +\hspace*{0.5in} & +\hspace*{0.3in} & +\hspace*{0.1in} & +\hspace*{0.1in} & +\hspace*{0.5in} & +\hspace*{0.5in} \\ + & +\instbitrange{31}{27} & +\instbitrange{26}{25} & +\instbitrange{24}{20} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbit{11} & +\instbit{10} & +\instbitrange{9}{5} & +\instbitrange{4}{0} \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode5} & +\multicolumn{8}{c|}{jump target} & J-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{6}{c|}{LUI-immediate} & LUI-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & I-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rb} & +\multicolumn{2}{c|}{funct4} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rc} & RSH-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{3}{c|}{funct5} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rc} & R4-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{4}{c|}{funct10} & +\multicolumn{1}{c|}{rc} & R-type \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Unimplemented Instruction} & \\ +\cline{2-10} + + +& +\multicolumn{9}{|c|}{00000000000000000000000000000000} & UNIMP \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Control Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{11000} & +\multicolumn{8}{c|}{imm27} & J imm27 \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{11001} & +\multicolumn{8}{c|}{imm27} & JAL imm27 \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{xc} & JALR.C xc,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000001} & +\multicolumn{1}{c|}{xc} & JALR.R xc,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000010} & +\multicolumn{1}{c|}{xc} & JALR.J xc,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm} & BEQ xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm} & BNE xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm} & BLT xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm} & BLTU xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{100} & +\multicolumn{4}{c|}{imm} & BLE xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{101} & +\multicolumn{4}{c|}{imm} & BLEU xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Memory Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm} & LB xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm} & LH xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm} & LW xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm} & LD xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{100} & +\multicolumn{4}{c|}{imm} & LBU xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{101} & +\multicolumn{4}{c|}{imm} & LHU xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{110} & +\multicolumn{4}{c|}{imm} & LWU xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{111} & +\multicolumn{4}{c|}{imm} & SYNCI xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm} & SB xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm} & SH xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm} & SW xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111001} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm} & SD xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Atomic Memory Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000000} & +\multicolumn{1}{c|}{xc} & AMOW.ADD xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000001} & +\multicolumn{1}{c|}{xc} & AMOW.SWAP xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000010} & +\multicolumn{1}{c|}{xc} & AMOW.AND xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000011} & +\multicolumn{1}{c|}{xc} & AMOW.OR xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000100} & +\multicolumn{1}{c|}{xc} & AMOW.MIN xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000101} & +\multicolumn{1}{c|}{xc} & AMOW.MAX xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000110} & +\multicolumn{1}{c|}{xc} & AMOW.MINU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000111} & +\multicolumn{1}{c|}{xc} & AMOW.MAXU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000000} & +\multicolumn{1}{c|}{xc} & AMO.ADD xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000001} & +\multicolumn{1}{c|}{xc} & AMO.SWAP xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000010} & +\multicolumn{1}{c|}{xc} & AMO.AND xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000011} & +\multicolumn{1}{c|}{xc} & AMO.OR xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000100} & +\multicolumn{1}{c|}{xc} & AMO.MIN xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000101} & +\multicolumn{1}{c|}{xc} & AMO.MAX xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000110} & +\multicolumn{1}{c|}{xc} & AMO.MINU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000111} & +\multicolumn{1}{c|}{xc} & AMO.MAXU xc,xb,xa \\ +\cline{2-10} + + +\end{tabular} +\end{center} +\end{small} + +\label{instr-table} +\end{table} + + +\newpage + +\begin{table}[p] +\begin{small} +\begin{center} +\begin{tabular}{rcccccccccl} + & +\hspace*{0.6in} & +\hspace*{0.2in} & +\hspace*{0.5in} & +\hspace*{0.5in} & +\hspace*{0.3in} & +\hspace*{0.1in} & +\hspace*{0.1in} & +\hspace*{0.5in} & +\hspace*{0.5in} \\ + & +\instbitrange{31}{27} & +\instbitrange{26}{25} & +\instbitrange{24}{20} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbit{11} & +\instbit{10} & +\instbitrange{9}{5} & +\instbitrange{4}{0} \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode5} & +\multicolumn{8}{c|}{jump target} & J-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{6}{c|}{LUI-immediate} & LUI-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & I-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rb} & +\multicolumn{2}{c|}{funct4} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rc} & RSH-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{3}{c|}{funct5} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rc} & R4-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{4}{c|}{funct10} & +\multicolumn{1}{c|}{rc} & R-type \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Integer Compute Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110001} & +\multicolumn{1}{c|}{xa} & +\multicolumn{6}{c|}{imm20} & LUI xa,imm20 \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110100} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm} & ADDI xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110100} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm} & SLTI xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110100} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{010} & +\multicolumn{4}{c|}{imm} & SLTIU xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110100} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{011} & +\multicolumn{4}{c|}{imm} & ANDI xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110100} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{100} & +\multicolumn{4}{c|}{imm} & ORI xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110100} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{101} & +\multicolumn{4}{c|}{imm} & XORI xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{xc} & ADD xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000001} & +\multicolumn{1}{c|}{xc} & SUB xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000010} & +\multicolumn{1}{c|}{xc} & SLT xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000011} & +\multicolumn{1}{c|}{xc} & SLTU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000100} & +\multicolumn{1}{c|}{xc} & AND xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000101} & +\multicolumn{1}{c|}{xc} & OR xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000110} & +\multicolumn{1}{c|}{xc} & XOR xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000111} & +\multicolumn{1}{c|}{xc} & NOR xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000000} & +\multicolumn{1}{c|}{xc} & MUL xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000010} & +\multicolumn{1}{c|}{xc} & MULH xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000011} & +\multicolumn{1}{c|}{xc} & MULHU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000100} & +\multicolumn{1}{c|}{xc} & DIV xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000101} & +\multicolumn{1}{c|}{xc} & DIVU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000110} & +\multicolumn{1}{c|}{xc} & REM xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000111} & +\multicolumn{1}{c|}{xc} & REMU xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000001} & +\multicolumn{1}{c|}{xc} & SLLV xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000010} & +\multicolumn{1}{c|}{xc} & SRLV xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000011} & +\multicolumn{1}{c|}{xc} & SRAV xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{2}{c|}{1010} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{xc} & SLL xc,xb,shamt \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{2}{c|}{1100} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{xc} & SRL xc,xb,shamt \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110101} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{2}{c|}{1110} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{xc} & SRA xc,xb,shamt \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf 32-bit Integer Compute Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110110} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm} & ADDIW xa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{xc} & ADDW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0000000001} & +\multicolumn{1}{c|}{xc} & SUBW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000000} & +\multicolumn{1}{c|}{xc} & MULW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000010} & +\multicolumn{1}{c|}{xc} & MULHW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000011} & +\multicolumn{1}{c|}{xc} & MULHUW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000100} & +\multicolumn{1}{c|}{xc} & DIVW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000101} & +\multicolumn{1}{c|}{xc} & DIVUW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000110} & +\multicolumn{1}{c|}{xc} & REMW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0010000111} & +\multicolumn{1}{c|}{xc} & REMUW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000001} & +\multicolumn{1}{c|}{xc} & SLLVW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000010} & +\multicolumn{1}{c|}{xc} & SRLVW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000011} & +\multicolumn{1}{c|}{xc} & SRAVW xc,xb,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{2}{c|}{1010} & +\multicolumn{1}{c|}{0} & +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{xc} & SLLW xc,xb,shamtw \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{2}{c|}{1100} & +\multicolumn{1}{c|}{0} & +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{xc} & SRLW xc,xb,shamtw \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1110111} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{2}{c|}{1110} & +\multicolumn{1}{c|}{0} & +\multicolumn{1}{c|}{shamtw} & +\multicolumn{1}{c|}{xc} & SRAW xc,xb,shamtw \\ +\cline{2-10} + + +\end{tabular} +\end{center} +\end{small} + +\label{instr-table} +\end{table} + + +\newpage + +\begin{table}[p] +\begin{small} +\begin{center} +\begin{tabular}{rcccccccccl} + & +\hspace*{0.6in} & +\hspace*{0.2in} & +\hspace*{0.5in} & +\hspace*{0.5in} & +\hspace*{0.3in} & +\hspace*{0.1in} & +\hspace*{0.1in} & +\hspace*{0.5in} & +\hspace*{0.5in} \\ + & +\instbitrange{31}{27} & +\instbitrange{26}{25} & +\instbitrange{24}{20} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbit{11} & +\instbit{10} & +\instbitrange{9}{5} & +\instbitrange{4}{0} \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode5} & +\multicolumn{8}{c|}{jump target} & J-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{6}{c|}{LUI-immediate} & LUI-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & I-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rb} & +\multicolumn{2}{c|}{funct4} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rc} & RSH-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{3}{c|}{funct5} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rc} & R4-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{4}{c|}{funct10} & +\multicolumn{1}{c|}{rc} & R-type \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Floating Point Memory Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101001} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{000} & +\multicolumn{4}{c|}{imm} & L.S fa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101001} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{110} & +\multicolumn{4}{c|}{imm} & L.D fa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101001} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{001} & +\multicolumn{4}{c|}{imm} & S.S fa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101001} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{1}{c|}{111} & +\multicolumn{4}{c|}{imm} & S.D fa,xb,imm \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Floating Point Compute Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{fc} & ADD.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000001} & +\multicolumn{1}{c|}{fc} & SUB.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000010} & +\multicolumn{1}{c|}{fc} & MUL.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000011} & +\multicolumn{1}{c|}{fc} & DIV.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000100} & +\multicolumn{1}{c|}{fc} & SQRT.S fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000101} & +\multicolumn{1}{c|}{fc} & SGNINJ.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000110} & +\multicolumn{1}{c|}{fc} & SGNINJN.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0000000111} & +\multicolumn{1}{c|}{fc} & SGNMUL.S fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000000} & +\multicolumn{1}{c|}{fc} & ADD.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000001} & +\multicolumn{1}{c|}{fc} & SUB.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000010} & +\multicolumn{1}{c|}{fc} & MUL.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000011} & +\multicolumn{1}{c|}{fc} & DIV.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100000100} & +\multicolumn{1}{c|}{fc} & SQRT.D fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000101} & +\multicolumn{1}{c|}{fc} & SGNINJ.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000110} & +\multicolumn{1}{c|}{fc} & SGNINJN.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1100000111} & +\multicolumn{1}{c|}{fc} & SGNMUL.D fc,fb,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{00000} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & MADD.S fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{00001} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & MSUB.S fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{00010} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & NMADD.S fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{00011} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & NMSUB.S fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{11000} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & MADD.D fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{11001} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & MSUB.D fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{11010} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & NMADD.D fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101011} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{3}{c|}{11011} & +\multicolumn{1}{c|}{fd} & +\multicolumn{1}{c|}{fc} & NMSUB.D fc,fb,fa,fd \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Floating Point Compare Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0001000001} & +\multicolumn{1}{c|}{xc} & C.EQ.S xc,fa,fb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0001000010} & +\multicolumn{1}{c|}{xc} & C.LT.S xc,fa,fb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{0001000011} & +\multicolumn{1}{c|}{xc} & C.LE.S xc,fa,fb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1101000001} & +\multicolumn{1}{c|}{xc} & C.EQ.D xc,fa,fb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1101000010} & +\multicolumn{1}{c|}{xc} & C.LT.D xc,fa,fb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{fb} & +\multicolumn{4}{c|}{1101000011} & +\multicolumn{1}{c|}{xc} & C.LE.D xc,fa,fb \\ +\cline{2-10} + + +\end{tabular} +\end{center} +\end{small} + +\label{instr-table} +\end{table} + + +\newpage + +\begin{table}[p] +\begin{small} +\begin{center} +\begin{tabular}{rcccccccccl} + & +\hspace*{0.6in} & +\hspace*{0.2in} & +\hspace*{0.5in} & +\hspace*{0.5in} & +\hspace*{0.3in} & +\hspace*{0.1in} & +\hspace*{0.1in} & +\hspace*{0.5in} & +\hspace*{0.5in} \\ + & +\instbitrange{31}{27} & +\instbitrange{26}{25} & +\instbitrange{24}{20} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbit{11} & +\instbit{10} & +\instbitrange{9}{5} & +\instbitrange{4}{0} \\ +\cline{2-10} +& +\multicolumn{1}{|c|}{opcode5} & +\multicolumn{8}{c|}{jump target} & J-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{6}{c|}{LUI-immediate} & LUI-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{4}{c|}{immediate} & I-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{rb} & +\multicolumn{2}{c|}{funct4} & +\multicolumn{2}{c|}{shamt} & +\multicolumn{1}{c|}{rc} & RSH-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{3}{c|}{funct5} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{rc} & R4-type \\ +\cline{2-10} +& +\multicolumn{2}{|c|}{opcode} & +\multicolumn{1}{c|}{ra} & +\multicolumn{1}{c|}{rb} & +\multicolumn{4}{c|}{funct10} & +\multicolumn{1}{c|}{rc} & R-type \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Integer/Floating Point Moves\&Conversion Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100000} & +\multicolumn{1}{c|}{fc} & TRUNC.L.S fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100001} & +\multicolumn{1}{c|}{fc} & TRUNCU.L.S fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100010} & +\multicolumn{1}{c|}{fc} & TRUNC.W.S fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100011} & +\multicolumn{1}{c|}{fc} & TRUNCU.W.S fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100100} & +\multicolumn{1}{c|}{fc} & CVT.S.L fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100101} & +\multicolumn{1}{c|}{fc} & CVTU.S.L fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100110} & +\multicolumn{1}{c|}{fc} & CVT.S.W fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000100111} & +\multicolumn{1}{c|}{fc} & CVTU.S.W fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000110011} & +\multicolumn{1}{c|}{fc} & CVT.S.D fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100000} & +\multicolumn{1}{c|}{fc} & TRUNC.L.D fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100001} & +\multicolumn{1}{c|}{fc} & TRUNCU.L.D fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100010} & +\multicolumn{1}{c|}{fc} & TRUNC.W.D fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100011} & +\multicolumn{1}{c|}{fc} & TRUNCU.W.D fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100100} & +\multicolumn{1}{c|}{fc} & CVT.D.L fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100101} & +\multicolumn{1}{c|}{fc} & CVTU.D.L fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100110} & +\multicolumn{1}{c|}{fc} & CVT.D.W fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100100111} & +\multicolumn{1}{c|}{fc} & CVTU.D.W fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101000} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100110000} & +\multicolumn{1}{c|}{fc} & CVT.D.S fc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{xc} & MFF.S xc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{c|}{fa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100000000} & +\multicolumn{1}{c|}{xc} & MFF.D xc,fa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0001000000} & +\multicolumn{1}{c|}{fc} & MTF.S fc,xa \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1101010} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1101000000} & +\multicolumn{1}{c|}{fc} & MTF.D fc,xa \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Miscellaneous Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0010000000} & +\multicolumn{1}{c|}{xc} & RDPC xc \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0100000000} & +\multicolumn{1}{c|}{xc} & MFCR xc,xb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{0110000000} & +\multicolumn{1}{c|}{00000} & MTCR xa,xb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1000000000} & +\multicolumn{1}{c|}{00000} & SYNC \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1010000000} & +\multicolumn{1}{c|}{00000} & SYSCALL \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111011} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1100000000} & +\multicolumn{1}{c|}{00000} & BREAK \\ +\cline{2-10} + + +& +\multicolumn{9}{c}{} & \\ +& +\multicolumn{9}{c}{\bf Privileged Instructions} & \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111110} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000000} & +\multicolumn{1}{c|}{xc} & EI xc \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111110} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0010000000} & +\multicolumn{1}{c|}{xc} & DI xc \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111110} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0100000000} & +\multicolumn{1}{c|}{00000} & ERET \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111110} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1000000000} & +\multicolumn{1}{c|}{xc} & MFPCR xc,xb \\ +\cline{2-10} + + +& +\multicolumn{2}{|c|}{1111110} & +\multicolumn{1}{c|}{xa} & +\multicolumn{1}{c|}{xb} & +\multicolumn{4}{c|}{1010000000} & +\multicolumn{1}{c|}{00000} & MTPCR xa,xb \\ +\cline{2-10} + + +\end{tabular} +\end{center} +\end{small} +\caption{Instruction listing for RISC-V} +\label{instr-table} +\end{table} + @@ -4,188 +4,189 @@ # <opcode> is given by specifying one or more range/value pairs: # highbit..lowbit=value (e.g. 31..25=0x45 14..12=0x0) # -# <args> is one of ra, rb, rc, rd, imm, imm20, imm27, shamt, shamtw - -unimp 31..0=0 - -j 31..27=0x18 imm27 # opcodes 0x60-0x64 -jal 31..27=0x19 imm27 # opcodes 0x64-0x68 - -lui 31..25=0x71 ra imm20 - -beq 31..25=0x73 14..12=0 ra rb imm -bne 31..25=0x73 14..12=1 ra rb imm -blt 31..25=0x73 14..12=2 ra rb imm -bltu 31..25=0x73 14..12=3 ra rb imm -ble 31..25=0x73 14..12=4 ra rb imm -bleu 31..25=0x73 14..12=5 ra rb imm - -addi 31..25=0x74 14..12=0 ra rb imm -addiw 31..25=0x74 14..12=1 ra rb imm -slti 31..25=0x74 14..12=2 ra rb imm -sltiu 31..25=0x74 14..12=3 ra rb imm -andi 31..25=0x74 14..12=4 ra rb imm -ori 31..25=0x74 14..12=5 ra rb imm -xori 31..25=0x74 14..12=6 ra rb imm - -add 31..25=0x75 14..12=0 11..5=0 rc rb ra -sub 31..25=0x75 14..12=0 11..5=1 rc rb ra -slt 31..25=0x75 14..12=0 11..5=2 rc rb ra -sltu 31..25=0x75 14..12=0 11..5=3 rc rb ra -and 31..25=0x75 14..12=0 11..5=4 rc rb ra -or 31..25=0x75 14..12=0 11..5=5 rc rb ra -xor 31..25=0x75 14..12=0 11..5=6 rc rb ra -nor 31..25=0x75 14..12=0 11..5=7 rc rb ra - -mul 31..25=0x75 14..12=1 11..5=0 rc rb ra -mulh 31..25=0x75 14..12=1 11..5=2 rc rb ra -mulhu 31..25=0x75 14..12=1 11..5=3 rc rb ra -div 31..25=0x75 14..12=1 11..5=4 rc rb ra -divu 31..25=0x75 14..12=1 11..5=5 rc rb ra -rem 31..25=0x75 14..12=1 11..5=6 rc rb ra -remu 31..25=0x75 14..12=1 11..5=7 rc rb ra - -sllv 31..25=0x75 14..12=4 11..5=1 rc rb ra -srlv 31..25=0x75 14..12=4 11..5=2 rc rb ra -srav 31..25=0x75 14..12=4 11..5=3 rc rb ra -sll 31..25=0x75 14..12=5 11=0 24..20=0 rc rb shamt -srl 31..25=0x75 14..12=6 11=0 24..20=0 rc rb shamt -sra 31..25=0x75 14..12=7 11=0 24..20=0 rc rb shamt - -addw 31..25=0x76 14..12=0 11..5=0 rc rb ra -subw 31..25=0x76 14..12=0 11..5=1 rc rb ra - -mulw 31..25=0x76 14..12=1 11..5=0 rc rb ra -mulhw 31..25=0x76 14..12=1 11..5=2 rc rb ra -mulhuw 31..25=0x76 14..12=1 11..5=3 rc rb ra -divw 31..25=0x76 14..12=1 11..5=4 rc rb ra -divuw 31..25=0x76 14..12=1 11..5=5 rc rb ra -remw 31..25=0x76 14..12=1 11..5=6 rc rb ra -remuw 31..25=0x76 14..12=1 11..5=7 rc rb ra - -sllvw 31..25=0x76 14..12=4 11..5=1 rc rb ra -srlvw 31..25=0x76 14..12=4 11..5=2 rc rb ra -sravw 31..25=0x76 14..12=4 11..5=3 rc rb ra -sllw 31..25=0x76 14..12=5 11..10=0 24..20=0 rc rb shamtw -srlw 31..25=0x76 14..12=6 11..10=0 24..20=0 rc rb shamtw -sraw 31..25=0x76 14..12=7 11..10=0 24..20=0 rc rb shamtw - -lb 31..25=0x78 14..12=0 rb ra imm -lh 31..25=0x78 14..12=1 rb ra imm -lw 31..25=0x78 14..12=2 rb ra imm -ld 31..25=0x78 14..12=3 rb ra imm -lbu 31..25=0x78 14..12=4 rb ra imm -lhu 31..25=0x78 14..12=5 rb ra imm -lwu 31..25=0x78 14..12=6 rb ra imm -synci 31..25=0x78 14..12=7 24..20=0 rb imm - -sb 31..25=0x79 14..12=0 rb ra imm -sh 31..25=0x79 14..12=1 rb ra imm -sw 31..25=0x79 14..12=2 rb ra imm -sd 31..25=0x79 14..12=3 rb ra imm - -amow.add 31..25=0x7A 14..12=2 11..5=0 rc rb ra -amow.swap 31..25=0x7A 14..12=2 11..5=1 rc rb ra -amow.and 31..25=0x7A 14..12=2 11..5=2 rc rb ra -amow.or 31..25=0x7A 14..12=2 11..5=3 rc rb ra -amow.min 31..25=0x7A 14..12=2 11..5=4 rc rb ra -amow.max 31..25=0x7A 14..12=2 11..5=5 rc rb ra -amow.minu 31..25=0x7A 14..12=2 11..5=6 rc rb ra -amow.maxu 31..25=0x7A 14..12=2 11..5=7 rc rb ra - -amo.add 31..25=0x7A 14..12=3 11..5=0 rc rb ra -amo.swap 31..25=0x7A 14..12=3 11..5=1 rc rb ra -amo.and 31..25=0x7A 14..12=3 11..5=2 rc rb ra -amo.or 31..25=0x7A 14..12=3 11..5=3 rc rb ra -amo.min 31..25=0x7A 14..12=3 11..5=4 rc rb ra -amo.max 31..25=0x7A 14..12=3 11..5=5 rc rb ra -amo.minu 31..25=0x7A 14..12=3 11..5=6 rc rb ra -amo.maxu 31..25=0x7A 14..12=3 11..5=7 rc rb ra - -jalr.c 31..25=0x7B 19..15=0 14..12=0 11..5=0 ra rc -jalr.r 31..25=0x7B 19..15=0 14..12=0 11..5=1 ra rc -jalr.j 31..25=0x7B 19..15=0 14..12=0 11..5=2 ra rc -rdpc 31..25=0x7B 24..15=0 14..12=1 11..5=0 rc -mfcr 31..25=0x7B 24..20=0 14..12=2 11..5=0 rc rb -mtcr 31..25=0x7B 14..12=3 11..0=0 ra rb -sync 31..25=0x7B 24..15=0 14..12=4 11..0=0 -syscall 31..25=0x7B 24..15=0 14..12=5 11..0=0 -break 31..25=0x7B 24..15=0 14..12=6 11..0=0 - -ei 31..25=0x7E 14..12=0 24..15=0 11..5=0 rc -di 31..25=0x7E 14..12=1 24..15=0 11..5=0 rc -eret 31..25=0x7E 14..12=2 24..15=0 11..0=0 -mfpcr 31..25=0x7E 14..12=4 24..20=0 11..5=0 rc rb -mtpcr 31..25=0x7E 14..12=5 11..0=0 ra rb +# <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw + +unimp 31..0=0 + +j 31..27=0x18 imm27 # opcodes 0x60-0x64 +jal 31..27=0x19 imm27 # opcodes 0x64-0x68 + +lui 31..25=0x71 xa imm20 + +beq 31..25=0x73 14..12=0 xa xb imm +bne 31..25=0x73 14..12=1 xa xb imm +blt 31..25=0x73 14..12=2 xa xb imm +bltu 31..25=0x73 14..12=3 xa xb imm +ble 31..25=0x73 14..12=4 xa xb imm +bleu 31..25=0x73 14..12=5 xa xb imm + +addi 31..25=0x74 14..12=0 xa xb imm +slti 31..25=0x74 14..12=1 xa xb imm +sltiu 31..25=0x74 14..12=2 xa xb imm +andi 31..25=0x74 14..12=3 xa xb imm +ori 31..25=0x74 14..12=4 xa xb imm +xori 31..25=0x74 14..12=5 xa xb imm + +add 31..25=0x75 14..12=0 11..5=0 xc xb xa +sub 31..25=0x75 14..12=0 11..5=1 xc xb xa +slt 31..25=0x75 14..12=0 11..5=2 xc xb xa +sltu 31..25=0x75 14..12=0 11..5=3 xc xb xa +and 31..25=0x75 14..12=0 11..5=4 xc xb xa +or 31..25=0x75 14..12=0 11..5=5 xc xb xa +xor 31..25=0x75 14..12=0 11..5=6 xc xb xa +nor 31..25=0x75 14..12=0 11..5=7 xc xb xa + +mul 31..25=0x75 14..12=1 11..5=0 xc xb xa +mulh 31..25=0x75 14..12=1 11..5=2 xc xb xa +mulhu 31..25=0x75 14..12=1 11..5=3 xc xb xa +div 31..25=0x75 14..12=1 11..5=4 xc xb xa +divu 31..25=0x75 14..12=1 11..5=5 xc xb xa +rem 31..25=0x75 14..12=1 11..5=6 xc xb xa +remu 31..25=0x75 14..12=1 11..5=7 xc xb xa + +sllv 31..25=0x75 14..12=4 11..5=1 xc xb xa +srlv 31..25=0x75 14..12=4 11..5=2 xc xb xa +srav 31..25=0x75 14..12=4 11..5=3 xc xb xa +sll 31..25=0x75 14..12=5 11=0 24..20=0 xc xb shamt +srl 31..25=0x75 14..12=6 11=0 24..20=0 xc xb shamt +sra 31..25=0x75 14..12=7 11=0 24..20=0 xc xb shamt + +addiw 31..25=0x76 14..12=0 xa xb imm + +addw 31..25=0x77 14..12=0 11..5=0 xc xb xa +subw 31..25=0x77 14..12=0 11..5=1 xc xb xa + +mulw 31..25=0x77 14..12=1 11..5=0 xc xb xa +mulhw 31..25=0x77 14..12=1 11..5=2 xc xb xa +mulhuw 31..25=0x77 14..12=1 11..5=3 xc xb xa +divw 31..25=0x77 14..12=1 11..5=4 xc xb xa +divuw 31..25=0x77 14..12=1 11..5=5 xc xb xa +remw 31..25=0x77 14..12=1 11..5=6 xc xb xa +remuw 31..25=0x77 14..12=1 11..5=7 xc xb xa + +sllvw 31..25=0x77 14..12=4 11..5=1 xc xb xa +srlvw 31..25=0x77 14..12=4 11..5=2 xc xb xa +sravw 31..25=0x77 14..12=4 11..5=3 xc xb xa +sllw 31..25=0x77 14..12=5 11..10=0 24..20=0 xc xb shamtw +srlw 31..25=0x77 14..12=6 11..10=0 24..20=0 xc xb shamtw +sraw 31..25=0x77 14..12=7 11..10=0 24..20=0 xc xb shamtw + +lb 31..25=0x78 14..12=0 xa xb imm +lh 31..25=0x78 14..12=1 xa xb imm +lw 31..25=0x78 14..12=2 xa xb imm +ld 31..25=0x78 14..12=3 xa xb imm +lbu 31..25=0x78 14..12=4 xa xb imm +lhu 31..25=0x78 14..12=5 xa xb imm +lwu 31..25=0x78 14..12=6 xa xb imm +synci 31..25=0x78 14..12=7 24..20=0 xb imm + +sb 31..25=0x79 14..12=0 xa xb imm +sh 31..25=0x79 14..12=1 xa xb imm +sw 31..25=0x79 14..12=2 xa xb imm +sd 31..25=0x79 14..12=3 xa xb imm + +amow.add 31..25=0x7A 14..12=2 11..5=0 xc xb xa +amow.swap 31..25=0x7A 14..12=2 11..5=1 xc xb xa +amow.and 31..25=0x7A 14..12=2 11..5=2 xc xb xa +amow.or 31..25=0x7A 14..12=2 11..5=3 xc xb xa +amow.min 31..25=0x7A 14..12=2 11..5=4 xc xb xa +amow.max 31..25=0x7A 14..12=2 11..5=5 xc xb xa +amow.minu 31..25=0x7A 14..12=2 11..5=6 xc xb xa +amow.maxu 31..25=0x7A 14..12=2 11..5=7 xc xb xa + +amo.add 31..25=0x7A 14..12=3 11..5=0 xc xb xa +amo.swap 31..25=0x7A 14..12=3 11..5=1 xc xb xa +amo.and 31..25=0x7A 14..12=3 11..5=2 xc xb xa +amo.or 31..25=0x7A 14..12=3 11..5=3 xc xb xa +amo.min 31..25=0x7A 14..12=3 11..5=4 xc xb xa +amo.max 31..25=0x7A 14..12=3 11..5=5 xc xb xa +amo.minu 31..25=0x7A 14..12=3 11..5=6 xc xb xa +amo.maxu 31..25=0x7A 14..12=3 11..5=7 xc xb xa + +jalr.c 31..25=0x7B 19..15=0 14..12=0 11..5=0 xc xa +jalr.r 31..25=0x7B 19..15=0 14..12=0 11..5=1 xc xa +jalr.j 31..25=0x7B 19..15=0 14..12=0 11..5=2 xc xa +rdpc 31..25=0x7B 24..15=0 14..12=1 11..5=0 xc +mfcr 31..25=0x7B 24..20=0 14..12=2 11..5=0 xc xb +mtcr 31..25=0x7B 14..12=3 11..0=0 xa xb +sync 31..25=0x7B 24..15=0 14..12=4 11..0=0 +syscall 31..25=0x7B 24..15=0 14..12=5 11..0=0 +break 31..25=0x7B 24..15=0 14..12=6 11..0=0 + +ei 31..25=0x7E 14..12=0 24..15=0 11..5=0 xc +di 31..25=0x7E 14..12=1 24..15=0 11..5=0 xc +eret 31..25=0x7E 14..12=2 24..15=0 11..0=0 +mfpcr 31..25=0x7E 14..12=4 24..20=0 11..5=0 xc xb +mtpcr 31..25=0x7E 14..12=5 11..0=0 xa xb # 0x7F is reserved for 64-bit-long instructions -add.s 31..25=0x68 14..12=0 11..10=0 9..5=0 rc rb ra -sub.s 31..25=0x68 14..12=0 11..10=0 9..5=1 rc rb ra -mul.s 31..25=0x68 14..12=0 11..10=0 9..5=2 rc rb ra -div.s 31..25=0x68 14..12=0 11..10=0 9..5=3 rc rb ra -sqrt.s 31..25=0x68 14..12=0 11..10=0 9..5=4 19..15=0 rc ra -sgninj.s 31..25=0x68 14..12=0 11..10=0 9..5=5 rc rb ra -sgninjn.s 31..25=0x68 14..12=0 11..10=0 9..5=6 rc rb ra -sgnmul.s 31..25=0x68 14..12=0 11..10=0 9..5=7 rc rb ra - -add.d 31..25=0x68 14..12=0 11..10=3 9..5=0 rc rb ra -sub.d 31..25=0x68 14..12=0 11..10=3 9..5=1 rc rb ra -mul.d 31..25=0x68 14..12=0 11..10=3 9..5=2 rc rb ra -div.d 31..25=0x68 14..12=0 11..10=3 9..5=3 rc rb ra -sqrt.d 31..25=0x68 14..12=0 11..10=3 9..5=4 19..15=0 rc ra -sgninj.d 31..25=0x68 14..12=0 11..10=3 9..5=5 rc rb ra -sgninjn.d 31..25=0x68 14..12=0 11..10=3 9..5=6 rc rb ra -sgnmul.d 31..25=0x68 14..12=0 11..10=3 9..5=7 rc rb ra - -trunc.l.s 31..25=0x68 14..12=1 11..10=0 9..5=0 19..15=0 rc ra -truncu.l.s 31..25=0x68 14..12=1 11..10=0 9..5=1 19..15=0 rc ra -trunc.w.s 31..25=0x68 14..12=1 11..10=0 9..5=2 19..15=0 rc ra -truncu.w.s 31..25=0x68 14..12=1 11..10=0 9..5=3 19..15=0 rc ra - -trunc.l.d 31..25=0x68 14..12=1 11..10=3 9..5=0 19..15=0 rc ra -truncu.l.d 31..25=0x68 14..12=1 11..10=3 9..5=1 19..15=0 rc ra -trunc.w.d 31..25=0x68 14..12=1 11..10=3 9..5=2 19..15=0 rc ra -truncu.w.d 31..25=0x68 14..12=1 11..10=3 9..5=3 19..15=0 rc ra - -cvt.s.l 31..25=0x68 14..12=1 11..10=0 9..5=4 19..15=0 rc ra -cvtu.s.l 31..25=0x68 14..12=1 11..10=0 9..5=5 19..15=0 rc ra -cvt.s.w 31..25=0x68 14..12=1 11..10=0 9..5=6 19..15=0 rc ra -cvtu.s.w 31..25=0x68 14..12=1 11..10=0 9..5=7 19..15=0 rc ra - -cvt.d.l 31..25=0x68 14..12=1 11..10=3 9..5=4 19..15=0 rc ra -cvtu.d.l 31..25=0x68 14..12=1 11..10=3 9..5=5 19..15=0 rc ra -cvt.d.w 31..25=0x68 14..12=1 11..10=3 9..5=6 19..15=0 rc ra -cvtu.d.w 31..25=0x68 14..12=1 11..10=3 9..5=7 19..15=0 rc ra - -cvt.s.d 31..25=0x68 14..12=1 11..10=0 9..5=0x13 19..15=0 rc ra -cvt.d.s 31..25=0x68 14..12=1 11..10=3 9..5=0x10 19..15=0 rc ra - -c.eq.s 31..25=0x68 14..12=2 11..10=0 9..5=1 rc ra rb -c.lt.s 31..25=0x68 14..12=2 11..10=0 9..5=2 rc ra rb -c.le.s 31..25=0x68 14..12=2 11..10=0 9..5=3 rc ra rb - -c.eq.d 31..25=0x68 14..12=2 11..10=3 9..5=1 rc ra rb -c.lt.d 31..25=0x68 14..12=2 11..10=3 9..5=2 rc ra rb -c.le.d 31..25=0x68 14..12=2 11..10=3 9..5=3 rc ra rb - -l.s 31..25=0x69 14..12=2 rb ra imm -l.d 31..25=0x69 14..12=3 rb ra imm -s.s 31..25=0x69 14..12=6 rb ra imm -s.d 31..25=0x69 14..12=7 rb ra imm - -mff.s 31..25=0x6A 19..15=0 14..12=0 11..5=0 ra rc -mff.d 31..25=0x6A 19..15=0 14..12=1 11..5=0 ra rc -mtf.s 31..25=0x6A 19..15=0 14..12=4 11..5=0 ra rc -mtf.d 31..25=0x6A 19..15=0 14..12=5 11..5=0 ra rc - -madd.s 31..25=0x6B 14..12=0 11..10=0 rc rb ra rd -msub.s 31..25=0x6B 14..12=1 11..10=0 rc rb ra rd -nmadd.s 31..25=0x6B 14..12=2 11..10=0 rc rb ra rd -nmsub.s 31..25=0x6B 14..12=3 11..10=0 rc rb ra rd - -madd.d 31..25=0x6B 14..12=0 11..10=3 rc rb ra rd -msub.d 31..25=0x6B 14..12=1 11..10=3 rc rb ra rd -nmadd.d 31..25=0x6B 14..12=2 11..10=3 rc rb ra rd -nmsub.d 31..25=0x6B 14..12=3 11..10=3 rc rb ra rd +add.s 31..25=0x68 14..13=0 12..10=0 9..5=0 fc fb fa +sub.s 31..25=0x68 14..13=0 12..10=0 9..5=1 fc fb fa +mul.s 31..25=0x68 14..13=0 12..10=0 9..5=2 fc fb fa +div.s 31..25=0x68 14..13=0 12..10=0 9..5=3 fc fb fa +sqrt.s 31..25=0x68 14..13=0 12..10=0 9..5=4 19..15=0 fc fa +sgninj.s 31..25=0x68 14..13=0 12..10=0 9..5=5 fc fb fa +sgninjn.s 31..25=0x68 14..13=0 12..10=0 9..5=6 fc fb fa +sgnmul.s 31..25=0x68 14..13=0 12..10=0 9..5=7 fc fb fa + +add.d 31..25=0x68 14..13=3 12..10=0 9..5=0 fc fb fa +sub.d 31..25=0x68 14..13=3 12..10=0 9..5=1 fc fb fa +mul.d 31..25=0x68 14..13=3 12..10=0 9..5=2 fc fb fa +div.d 31..25=0x68 14..13=3 12..10=0 9..5=3 fc fb fa +sqrt.d 31..25=0x68 14..13=3 12..10=0 9..5=4 19..15=0 fc fa +sgninj.d 31..25=0x68 14..13=3 12..10=0 9..5=5 fc fb fa +sgninjn.d 31..25=0x68 14..13=3 12..10=0 9..5=6 fc fb fa +sgnmul.d 31..25=0x68 14..13=3 12..10=0 9..5=7 fc fb fa + +trunc.l.s 31..25=0x68 14..13=0 12..10=1 9..5=0 19..15=0 fc fa +truncu.l.s 31..25=0x68 14..13=0 12..10=1 9..5=1 19..15=0 fc fa +trunc.w.s 31..25=0x68 14..13=0 12..10=1 9..5=2 19..15=0 fc fa +truncu.w.s 31..25=0x68 14..13=0 12..10=1 9..5=3 19..15=0 fc fa + +trunc.l.d 31..25=0x68 14..13=3 12..10=1 9..5=0 19..15=0 fc fa +truncu.l.d 31..25=0x68 14..13=3 12..10=1 9..5=1 19..15=0 fc fa +trunc.w.d 31..25=0x68 14..13=3 12..10=1 9..5=2 19..15=0 fc fa +truncu.w.d 31..25=0x68 14..13=3 12..10=1 9..5=3 19..15=0 fc fa + +cvt.s.l 31..25=0x68 14..13=0 12..10=1 9..5=4 19..15=0 fc fa +cvtu.s.l 31..25=0x68 14..13=0 12..10=1 9..5=5 19..15=0 fc fa +cvt.s.w 31..25=0x68 14..13=0 12..10=1 9..5=6 19..15=0 fc fa +cvtu.s.w 31..25=0x68 14..13=0 12..10=1 9..5=7 19..15=0 fc fa + +cvt.d.l 31..25=0x68 14..13=3 12..10=1 9..5=4 19..15=0 fc fa +cvtu.d.l 31..25=0x68 14..13=3 12..10=1 9..5=5 19..15=0 fc fa +cvt.d.w 31..25=0x68 14..13=3 12..10=1 9..5=6 19..15=0 fc fa +cvtu.d.w 31..25=0x68 14..13=3 12..10=1 9..5=7 19..15=0 fc fa + +cvt.s.d 31..25=0x68 14..13=0 12..10=1 9..5=0x13 19..15=0 fc fa +cvt.d.s 31..25=0x68 14..13=3 12..10=1 9..5=0x10 19..15=0 fc fa + +c.eq.s 31..25=0x68 14..13=0 12..10=2 9..5=1 xc fa fb +c.lt.s 31..25=0x68 14..13=0 12..10=2 9..5=2 xc fa fb +c.le.s 31..25=0x68 14..13=0 12..10=2 9..5=3 xc fa fb + +c.eq.d 31..25=0x68 14..13=3 12..10=2 9..5=1 xc fa fb +c.lt.d 31..25=0x68 14..13=3 12..10=2 9..5=2 xc fa fb +c.le.d 31..25=0x68 14..13=3 12..10=2 9..5=3 xc fa fb + +l.s 31..25=0x69 14..13=0 12=0 fa xb imm +l.d 31..25=0x69 14..13=3 12=0 fa xb imm +s.s 31..25=0x69 14..13=0 12=1 fa xb imm +s.d 31..25=0x69 14..13=3 12=1 fa xb imm + +mff.s 31..25=0x6A 19..15=0 14..13=0 12..10=0 9..5=0 xc fa +mff.d 31..25=0x6A 19..15=0 14..13=3 12..10=0 9..5=0 xc fa +mtf.s 31..25=0x6A 19..15=0 14..13=0 12..10=2 9..5=0 fc xa +mtf.d 31..25=0x6A 19..15=0 14..13=3 12..10=2 9..5=0 fc xa + +madd.s 31..25=0x6B 14..13=0 12..10=0 fc fb fa fd +msub.s 31..25=0x6B 14..13=0 12..10=1 fc fb fa fd +nmadd.s 31..25=0x6B 14..13=0 12..10=2 fc fb fa fd +nmsub.s 31..25=0x6B 14..13=0 12..10=3 fc fb fa fd + +madd.d 31..25=0x6B 14..13=3 12..10=0 fc fb fa fd +msub.d 31..25=0x6B 14..13=3 12..10=1 fc fb fa fd +nmadd.d 31..25=0x6B 14..13=3 12..10=2 fc fb fa fd +nmsub.d 31..25=0x6B 14..13=3 12..10=3 fc fb fa fd diff --git a/parse-opcodes b/parse-opcodes index a2302d4..10ade79 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -4,161 +4,519 @@ import math import sys import tokenize +namelist = [] match = {} mask = {} +arguments = {} +types = {} -args = {} -args['ra'] = (24,20) -args['rb'] = (19,15) -args['rc'] = (4,0) -args['rd'] = (9,5) -args['imm27'] = (26,0) -args['imm20'] = (19,0) -args['imm'] = (11,0) -args['shamt'] = (10,5) -args['shamtw'] = (9,5) +arglut = {} +arglut['xa'] = (24,20) +arglut['xb'] = (19,15) +arglut['xc'] = (4,0) +arglut['fa'] = (24,20) +arglut['fb'] = (19,15) +arglut['fc'] = (4,0) +arglut['fd'] = (9,5) +arglut['imm27'] = (26,0) +arglut['imm20'] = (19,0) +arglut['imm'] = (11,0) +arglut['shamt'] = (10,5) +arglut['shamtw'] = (9,5) + +typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=rsh,7=rshw +typelut[0x00] = 0 +typelut[0x60] = 1 +typelut[0x64] = 1 +typelut[0x71] = 2 +typelut[0x73] = 3 +typelut[0x74] = 3 +typelut[0x75] = 4 +typelut[0x76] = 3 +typelut[0x77] = 4 +typelut[0x78] = 3 +typelut[0x79] = 3 +typelut[0x7a] = 4 +typelut[0x7b] = 4 +typelut[0x7e] = 4 +typelut[0x68] = 4 +typelut[0x69] = 3 +typelut[0x6a] = 4 +typelut[0x6b] = 5 def binary(n, digits=0): - rep = bin(n)[2:] - return rep if digits == 0 else ('0' * (digits - len(rep))) + rep + rep = bin(n)[2:] + return rep if digits == 0 else ('0' * (digits - len(rep))) + rep def make_disasm_table(match,mask): - print '/* Automatically generated by parse-opcodes */' - for name,match in match.iteritems(): - name2 = name.upper().replace('.','_') - print '#define MATCH_%s %s' % (name2, hex(match)) - print '#define MASK_%s %s' % (name2, hex(mask[name])) + print '/* Automatically generated by parse-opcodes */' + for name,match in match.iteritems(): + name2 = name.upper().replace('.','_') + print '#define MATCH_%s %s' % (name2, hex(match)) + print '#define MASK_%s %s' % (name2, hex(mask[name])) def make_switch(match,mask): - opcode_base = 25 - opcode_size = 7 - funct_base = 12 - funct_size = 3 - - opcode_mask = ((1<<(opcode_base+opcode_size))-(1<<opcode_base)) - funct_mask = ((1<<(funct_base+funct_size))-(1<<funct_base)) - - print '/* Automatically generated by parse-opcodes */' - print 'switch((insn.bits >> 0x%x) & 0x%x)' % (opcode_base,(1<<opcode_size)-1) - print '{' - - for opc in range(0,1<<opcode_size): - has_some_instruction = 0 - for name in match.iterkeys(): - if ((opc << opcode_base) & mask[name]) == (match[name] & mask[name] & opcode_mask): - has_some_instruction = 1 - if not has_some_instruction: continue - - print ' case 0x%x:' % opc - print ' {' - done = 0 - for name in match.iterkeys(): - name2 = name.replace('.','_') - # case 0: opcode fully describes insn - if ((opc << opcode_base) & mask[name]) == match[name] and (opcode_mask & mask[name]) == mask[name]: - print ' #include "insns/%s.h"' % name2 - done = 1 - break - - if not done: - print ' switch((insn.bits >> 0x%x) & 0x%x)' % (funct_base,(1<<funct_size)-1) - print ' {' - for funct in range(0,1<<funct_size): - has_some_instruction = 0 - for name in match.iterkeys(): - if (opc << opcode_base | funct << funct_base) == (match[name] & (opcode_mask | funct_mask)): - has_some_instruction = 1 - if not has_some_instruction: continue - print ' case 0x%x:' % funct - print ' {' - done = 0 - for name in match.iterkeys(): - name2 = name.replace('.','_') - # case 1: opcode + funct code completely describe insn - if ((opc << opcode_base | funct << funct_base) & mask[name]) == match[name] and ((opcode_mask | funct_mask) & mask[name]) == mask[name]: - print ' #include "insns/%s.h"' % name2 - print ' break;' - done = 1 - break - if not done: - for name in match.iterkeys(): - name2 = name.replace('.','_') - # case 2: general case: opcode + funct incompletely describe insn - if (opc << opcode_base | funct << funct_base) == (match[name] & (opcode_mask | funct_mask)): - print ' if((insn.bits & 0x%x) == 0x%x)' % (mask[name],match[name]) - print ' {' - print ' #include "insns/%s.h"' % name2 - print ' break;' - print ' }' - print ' #include "insns/unimp.h"' - print ' }' - print ' default:' - print ' {' - print ' #include "insns/unimp.h"' - print ' }' - print ' }' - print ' break;' - print ' }' - print ' default:' - print ' {' - print ' #include "insns/unimp.h"' - print ' }' - print '}' + opcode_base = 25 + opcode_size = 7 + funct_base = 12 + funct_size = 3 + + opcode_mask = ((1<<(opcode_base+opcode_size))-(1<<opcode_base)) + funct_mask = ((1<<(funct_base+funct_size))-(1<<funct_base)) + + print '/* Automatically generated by parse-opcodes */' + print 'switch((insn.bits >> 0x%x) & 0x%x)' % (opcode_base,(1<<opcode_size)-1) + print '{' + + for opc in range(0,1<<opcode_size): + has_some_instruction = 0 + for name in match.iterkeys(): + if ((opc << opcode_base) & mask[name]) == (match[name] & mask[name] & opcode_mask): + has_some_instruction = 1 + if not has_some_instruction: continue + + print ' case 0x%x:' % opc + print ' {' + done = 0 + for name in match.iterkeys(): + name2 = name.replace('.','_') + # case 0: opcode fully describes insn + if ((opc << opcode_base) & mask[name]) == match[name] and (opcode_mask & mask[name]) == mask[name]: + print ' #include "insns/%s.h"' % name2 + done = 1 + break + + if not done: + print ' switch((insn.bits >> 0x%x) & 0x%x)' % (funct_base,(1<<funct_size)-1) + print ' {' + for funct in range(0,1<<funct_size): + has_some_instruction = 0 + for name in match.iterkeys(): + if (opc << opcode_base | funct << funct_base) == (match[name] & (opcode_mask | funct_mask)): + has_some_instruction = 1 + if not has_some_instruction: continue + print ' case 0x%x:' % funct + print ' {' + done = 0 + for name in match.iterkeys(): + name2 = name.replace('.','_') + # case 1: opcode + funct code completely describe insn + if ((opc << opcode_base | funct << funct_base) & mask[name]) == match[name] and ((opcode_mask | funct_mask) & mask[name]) == mask[name]: + print ' #include "insns/%s.h"' % name2 + print ' break;' + done = 1 + break + if not done: + for name in match.iterkeys(): + name2 = name.replace('.','_') + # case 2: general case: opcode + funct incompletely describe insn + if (opc << opcode_base | funct << funct_base) == (match[name] & (opcode_mask | funct_mask)): + print ' if((insn.bits & 0x%x) == 0x%x)' % (mask[name],match[name]) + print ' {' + print ' #include "insns/%s.h"' % name2 + print ' break;' + print ' }' + print ' #include "insns/unimp.h"' + print ' }' + print ' default:' + print ' {' + print ' #include "insns/unimp.h"' + print ' }' + print ' }' + print ' break;' + print ' }' + print ' default:' + print ' {' + print ' #include "insns/unimp.h"' + print ' }' + print '}' + +def yank(num,start,len): + return (num >> start) & ((1 << len) - 1) + +def str_arg(arg0,arg1,match,arguments): + if arg0 in arguments: + return arg0 + elif arg1 in arguments: + return arg1 + else: + start = arglut[arg0][1] + len = arglut[arg0][0] - arglut[arg0][1] + 1 + return binary(yank(match,start,len),len) + +def str_inst(name,arguments): + ret = name.upper() + ' ' + for idx in range(len(arguments)): + ret = ret + arguments[idx] + if idx != len(arguments)-1: + ret = ret + ',' + return ret + +def print_unimp_type(name,match,arguments): + print """ +& +\\multicolumn{9}{|c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + '0'*32, \ + 'UNIMP' \ + ) + +def print_j_type(name,match,arguments): + print """ +& +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{8}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,27,5),5), \ + str_arg('imm27','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_lui_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{6}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + str_arg('xa','fa',match,arguments), \ + str_arg('imm20','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_i_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{4}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + str_arg('xa','fa',match,arguments), \ + str_arg('xb','fb',match,arguments), \ + binary(yank(match,12,3),3), \ + str_arg('imm','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_rsh_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{00000} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + str_arg('xb','',match,arguments), \ + binary(yank(match,11,4),4), \ + str_arg('shamt','',match,arguments), \ + str_arg('xc','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_rshw_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{00000} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{0} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + str_arg('xb','',match,arguments), \ + binary(yank(match,11,4),4), \ + str_arg('shamtw','',match,arguments), \ + str_arg('xc','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_r4_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{3}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + str_arg('fa','',match,arguments), \ + str_arg('fb','',match,arguments), \ + binary(yank(match,10,5),5), \ + str_arg('fd','',match,arguments), \ + str_arg('fc','',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_r_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{4}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,25,7),7), \ + str_arg('xa','fa',match,arguments), \ + str_arg('xb','fb',match,arguments), \ + binary(yank(match,5,10),10), \ + str_arg('xc','fc',match,arguments), \ + str_inst(name,arguments) \ + ) + +def print_header(): + print """ +\\newpage + +\\begin{table}[p] +\\begin{small} +\\begin{center} +\\begin{tabular}{rcccccccccl} + & +\\hspace*{0.6in} & +\\hspace*{0.2in} & +\\hspace*{0.5in} & +\\hspace*{0.5in} & +\\hspace*{0.3in} & +\\hspace*{0.1in} & +\\hspace*{0.1in} & +\\hspace*{0.5in} & +\\hspace*{0.5in} \\\\ + & +\\instbitrange{31}{27} & +\\instbitrange{26}{25} & +\\instbitrange{24}{20} & +\\instbitrange{19}{15} & +\\instbitrange{14}{12} & +\\instbit{11} & +\\instbit{10} & +\\instbitrange{9}{5} & +\\instbitrange{4}{0} \\\\ +\\cline{2-10} +& +\\multicolumn{1}{|c|}{opcode5} & +\\multicolumn{8}{c|}{jump target} & J-type \\\\ +\\cline{2-10} +& +\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{c|}{ra} & +\\multicolumn{6}{c|}{LUI-immediate} & LUI-type \\\\ +\\cline{2-10} +& +\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{c|}{ra} & +\\multicolumn{1}{c|}{rb} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{4}{c|}{immediate} & I-type \\\\ +\\cline{2-10} +& +\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{c|}{00000} & +\\multicolumn{1}{c|}{rb} & +\\multicolumn{2}{c|}{funct4} & +\\multicolumn{2}{c|}{shamt} & +\\multicolumn{1}{c|}{rc} & RSH-type \\\\ +\\cline{2-10} +& +\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{c|}{ra} & +\\multicolumn{1}{c|}{rb} & +\\multicolumn{3}{c|}{funct5} & +\\multicolumn{1}{c|}{rd} & +\\multicolumn{1}{c|}{rc} & R4-type \\\\ +\\cline{2-10} +& +\\multicolumn{2}{|c|}{opcode} & +\\multicolumn{1}{c|}{ra} & +\\multicolumn{1}{c|}{rb} & +\\multicolumn{4}{c|}{funct10} & +\\multicolumn{1}{c|}{rc} & R-type \\\\ +\\cline{2-10} + """ + +def print_subtitle(title): + print """ +& +\\multicolumn{9}{c}{} & \\\\ +& +\\multicolumn{9}{c}{\\bf %s} & \\\\ +\\cline{2-10} + """ % title + +def print_footer(caption): + print """ +\\end{tabular} +\\end{center} +\\end{small} +%s +\\label{instr-table} +\\end{table} + """ % (caption and '\\caption{Instruction listing for RISC-V}' or '') + +def print_insts(opcode,type,min,max): + for name in namelist: + if yank(match[name],25,7) == opcode: + if type == -1 or types[name] == type: + if types[name] == 0: + print_unimp_type(name,match[name],arguments[name]) + elif types[name] == 1: + print_j_type(name,match[name],arguments[name]) + elif types[name] == 2: + print_lui_type(name,match[name],arguments[name]) + elif types[name] == 3: + print_i_type(name,match[name],arguments[name]) + elif types[name] == 4 \ + and (min == -1 or yank(match[name],5,10) >= min) \ + and (max == -1 or yank(match[name],5,10) <= max): + print_r_type(name,match[name],arguments[name]) + elif types[name] == 5: + print_r4_type(name,match[name],arguments[name]) + elif types[name] == 6: + print_rsh_type(name,match[name],arguments[name]) + elif types[name] == 7: + print_rshw_type(name,match[name],arguments[name]) + +def make_latex_table(): + print_header() + print_subtitle('Unimplemented Instruction') + print_insts(0x00,-1,-1,-1) + print_subtitle('Control Instructions') + print_insts(0x60,-1,-1,-1) + print_insts(0x64,-1,-1,-1) + print_insts(0x7b,-1,0x000,0x002) + print_insts(0x73,-1,-1,-1) + print_subtitle('Memory Instructions') + print_insts(0x78,-1,-1,-1) + print_insts(0x79,-1,-1,-1) + print_subtitle('Atomic Memory Instructions') + print_insts(0x7a,-1,-1,-1) + print_footer(0) + + print_header() + print_subtitle('Integer Compute Instructions') + print_insts(0x71,-1,-1,-1) + print_insts(0x74,-1,-1,-1) + print_insts(0x75,-1,-1,-1) + print_subtitle('32-bit Integer Compute Instructions') + print_insts(0x76,-1,-1,-1) + print_insts(0x77,-1,-1,-1) + print_footer(0) + + print_header() + print_subtitle('Floating Point Memory Instructions') + print_insts(0x69,-1,-1,-1) + print_subtitle('Floating Point Compute Instructions') + print_insts(0x68,-1,0x000,0x01F) + print_insts(0x68,-1,0x300,0x31F) + print_insts(0x6b,-1,-1,-1) + print_subtitle('Floating Point Compare Instructions') + print_insts(0x68,-1,0x040,0x05F) + print_insts(0x68,-1,0x340,0x35F) + print_footer(0) + + print_header() + print_subtitle('Integer/Floating Point Moves\&Conversion Instructions') + print_insts(0x68,-1,0x020,0x03F) + print_insts(0x68,-1,0x320,0x33F) + print_insts(0x6a,-1,-1,-1) + print_subtitle('Miscellaneous Instructions') + print_insts(0x7b,-1,0x080,0x300) + print_subtitle('Privileged Instructions') + print_insts(0x7e,-1,-1,-1) + print_footer(1) for line in sys.stdin: - line = line.partition('#') - tokens = line[0].split() - - if len(tokens) == 0: - continue - assert len(tokens) >= 2 - - name = tokens[0] - mymatch = 0 - mymask = 0 - cover = 0 - - for token in tokens[1:len(tokens)]: - if len(token.split('=')) == 2: - tmp = token.split('=') - val = int(tmp[1],0) - if len(tmp[0].split('..')) == 2: - tmp = tmp[0].split('..') - hi = int(tmp[0]) - lo = int(tmp[1]) - if hi <= lo: - sys.exit("%s: bad range %d..%d" % (name,hi,lo)) - else: - hi = lo = int(tmp[0]) - if val >= (1 << (hi-lo+1)): - sys.exit("%s: bad value %d for range %d..%d" % (name,val,hi,lo)) - mymatch = mymatch | (val << lo) - mymask = mymask | ((1<<(hi+1))-(1<<lo)) - if cover & ((1<<(hi+1))-(1<<lo)): - sys.exit("%s: overspecified" % name) - cover = cover | ((1<<(hi+1))-(1<<lo)) - elif token in args: - if cover & ((1<<(args[token][0]+1))-(1<<args[token][1])): - sys.exit("%s: overspecified" % name) - cover = cover | ((1<<(args[token][0]+1))-(1<<args[token][1])) - else: - sys.exit("%s: unknown token %s" % (name,token)); - - if cover != 0xFFFFFFFF: - sys.exit("%s: not all bits are covered" % name) - - for name2,match2 in match.iteritems(): - if (match2 & mymask) == mymatch: - sys.exit("%s and %s overlap" % (name,name2)); - - mask[name] = mymask; - match[name] = mymatch; + line = line.partition('#') + tokens = line[0].split() + + if len(tokens) == 0: + continue + assert len(tokens) >= 2 + + name = tokens[0] + mymatch = 0 + mymask = 0 + cover = 0 + + if not name in arguments.keys(): + arguments[name] = [] + + for token in tokens[1:]: + if len(token.split('=')) == 2: + tmp = token.split('=') + val = int(tmp[1],0) + if len(tmp[0].split('..')) == 2: + tmp = tmp[0].split('..') + hi = int(tmp[0]) + lo = int(tmp[1]) + if hi <= lo: + sys.exit("%s: bad range %d..%d" % (name,hi,lo)) + else: + hi = lo = int(tmp[0]) + if val >= (1 << (hi-lo+1)): + sys.exit("%s: bad value %d for range %d..%d" % (name,val,hi,lo)) + mymatch = mymatch | (val << lo) + mymask = mymask | ((1<<(hi+1))-(1<<lo)) + if cover & ((1<<(hi+1))-(1<<lo)): + sys.exit("%s: overspecified" % name) + cover = cover | ((1<<(hi+1))-(1<<lo)) + elif token in arglut: + if cover & ((1<<(arglut[token][0]+1))-(1<<arglut[token][1])): + sys.exit("%s: overspecified" % name) + cover = cover | ((1<<(arglut[token][0]+1))-(1<<arglut[token][1])) + + arguments[name].append(token) + else: + sys.exit("%s: unknown token %s" % (name,token)) + + if cover != 0xFFFFFFFF: + sys.exit("%s: not all bits are covered" % name) + + for name2,match2 in match.iteritems(): + if (match2 & mymask) == mymatch: + sys.exit("%s and %s overlap" % (name,name2)) + + mask[name] = mymask + match[name] = mymatch + types[name] = typelut[yank(mymatch,25,7)] + if 'shamtw' in arguments[name]: + types[name] = 7 + elif 'shamt' in arguments[name]: + types[name] = 6 + namelist.append(name) if sys.argv[1] == '-tex': - make_latex_table(opcodes, ['Instructions encoded by opcode field','Instructions encoded by funct field when opcode = %(opcode)d'], ['opcodes','opcode%(opcode)d']) + make_latex_table() elif sys.argv[1] == '-disasm': - make_disasm_table(match,mask) + make_disasm_table(match,mask) elif sys.argv[1] == '-switch': - make_switch(match,mask) + make_switch(match,mask) else: - assert 0 + assert 0 diff --git a/update-opcodes b/update-opcodes index da603b5..be3d2cc 100755 --- a/update-opcodes +++ b/update-opcodes @@ -1,4 +1,4 @@ #!/bin/bash -#./parse-opcodes -tex < opcodes > ../doc/opcodes.tex +./parse-opcodes -tex < opcodes > instr-table.tex ./parse-opcodes -disasm < opcodes > ../xcc/src/include/opcode/mips-riscv-opc.h ./parse-opcodes -switch < opcodes > ../sim/riscv/execute.h |