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-rw-r--r--Makefile4
-rw-r--r--inst.v131
-rw-r--r--instr-table.tex8
-rw-r--r--opcodes194
-rw-r--r--opcodes-hwacha144
-rw-r--r--opcodes-rvc40
-rwxr-xr-xparse-opcodes8
7 files changed, 203 insertions, 326 deletions
diff --git a/Makefile b/Makefile
index 65f5cf6..eba19bb 100644
--- a/Makefile
+++ b/Makefile
@@ -11,8 +11,10 @@ $(ISASIM_H): opcodes parse-opcodes
$(PK_H): opcodes parse-opcodes
./parse-opcodes -disasm < $< > $@
-$(GAS_H): opcodes parse-opcodes
+$(GAS_H): opcodes opcodes-hwacha opcodes-rvc parse-opcodes
./parse-opcodes -disasm < $< > $@
+ ./parse-opcodes -disasm < opcodes-hwacha >> $@
+ ./parse-opcodes -disasm < opcodes-rvc >> $@
$(XCC_H): opcodes parse-opcodes
./parse-opcodes -disasm < $< > $@
diff --git a/inst.v b/inst.v
index 2d23432..5588ccd 100644
--- a/inst.v
+++ b/inst.v
@@ -140,11 +140,11 @@
`define FMAX_S 32'b???????????????11001000001010011
`define FMIN_D 32'b???????????????11000000011010011
`define FMAX_D 32'b???????????????11001000011010011
-`define MFTX_S 32'b??????????0000011100000001010011
-`define MFTX_D 32'b??????????0000011100000011010011
+`define FMV_X_S 32'b??????????0000011100000001010011
+`define FMV_X_D 32'b??????????0000011100000011010011
`define MFFSR 32'b?????000000000011101000001010011
-`define MXTF_S 32'b??????????0000011110000001010011
-`define MXTF_D 32'b??????????0000011110000011010011
+`define FMV_S_X 32'b??????????0000011110000001010011
+`define FMV_D_X 32'b??????????0000011110000011010011
`define MTFSR 32'b??????????0000011111000001010011
`define FLW 32'b??????????????????????0100000111
`define FLD 32'b??????????????????????0110000111
@@ -158,126 +158,3 @@
`define FMSUB_D 32'b???????????????????????011000111
`define FNMSUB_D 32'b???????????????????????011001011
`define FNMADD_D 32'b???????????????????????011001111
-`define STOP 32'b00000000000000000000000101110111
-`define UTIDX 32'b?????000000000000000000111110111
-`define MOVZ 32'b???????????????00000001011110111
-`define MOVN 32'b???????????????00000011011110111
-`define FMOVZ 32'b???????????????00000101011110111
-`define FMOVN 32'b???????????????00000111011110111
-`define VXCPTSAVE 32'b00000?????0000000000001101111011
-`define VXCPTRESTORE 32'b00000?????0000000000011101111011
-`define VXCPTKILL 32'b00000000000000000000101101111011
-`define VXCPTEVAC 32'b00000?????0000000010001101111011
-`define VXCPTHOLD 32'b00000000000000000010011101111011
-`define VENQCMD 32'b00000??????????00010101101111011
-`define VENQIMM1 32'b00000??????????00010111101111011
-`define VENQIMM2 32'b00000??????????00011001101111011
-`define VENQCNT 32'b00000??????????00011011101111011
-`define VLD 32'b??????????0000000000000110001011
-`define VLW 32'b??????????0000000000000100001011
-`define VLWU 32'b??????????0000000000001100001011
-`define VLH 32'b??????????0000000000000010001011
-`define VLHU 32'b??????????0000000000001010001011
-`define VLB 32'b??????????0000000000000000001011
-`define VLBU 32'b??????????0000000000001000001011
-`define VFLD 32'b??????????0000000000010110001011
-`define VFLW 32'b??????????0000000000010100001011
-`define VLSTD 32'b???????????????00001000110001011
-`define VLSTW 32'b???????????????00001000100001011
-`define VLSTWU 32'b???????????????00001001100001011
-`define VLSTH 32'b???????????????00001000010001011
-`define VLSTHU 32'b???????????????00001001010001011
-`define VLSTB 32'b???????????????00001000000001011
-`define VLSTBU 32'b???????????????00001001000001011
-`define VFLSTD 32'b???????????????00001010110001011
-`define VFLSTW 32'b???????????????00001010100001011
-`define VLSEGD 32'b???????????????00010000110001011
-`define VLSEGW 32'b???????????????00010000100001011
-`define VLSEGWU 32'b???????????????00010001100001011
-`define VLSEGH 32'b???????????????00010000010001011
-`define VLSEGHU 32'b???????????????00010001010001011
-`define VLSEGB 32'b???????????????00010000000001011
-`define VLSEGBU 32'b???????????????00010001000001011
-`define VFLSEGD 32'b???????????????00010010110001011
-`define VFLSEGW 32'b???????????????00010010100001011
-`define VLSEGSTD 32'b????????????????????100110001011
-`define VLSEGSTW 32'b????????????????????100100001011
-`define VLSEGSTWU 32'b????????????????????101100001011
-`define VLSEGSTH 32'b????????????????????100010001011
-`define VLSEGSTHU 32'b????????????????????101010001011
-`define VLSEGSTB 32'b????????????????????100000001011
-`define VLSEGSTBU 32'b????????????????????101000001011
-`define VFLSEGSTD 32'b????????????????????110110001011
-`define VFLSEGSTW 32'b????????????????????110100001011
-`define VSD 32'b??????????0000000000000110001111
-`define VSW 32'b??????????0000000000000100001111
-`define VSH 32'b??????????0000000000000010001111
-`define VSB 32'b??????????0000000000000000001111
-`define VFSD 32'b??????????0000000000010110001111
-`define VFSW 32'b??????????0000000000010100001111
-`define VSSTD 32'b???????????????00001000110001111
-`define VSSTW 32'b???????????????00001000100001111
-`define VSSTH 32'b???????????????00001000010001111
-`define VSSTB 32'b???????????????00001000000001111
-`define VFSSTD 32'b???????????????00001010110001111
-`define VFSSTW 32'b???????????????00001010100001111
-`define VSSEGD 32'b???????????????00010000110001111
-`define VSSEGW 32'b???????????????00010000100001111
-`define VSSEGH 32'b???????????????00010000010001111
-`define VSSEGB 32'b???????????????00010000000001111
-`define VFSSEGD 32'b???????????????00010010110001111
-`define VFSSEGW 32'b???????????????00010010100001111
-`define VSSEGSTD 32'b????????????????????100110001111
-`define VSSEGSTW 32'b????????????????????100100001111
-`define VSSEGSTH 32'b????????????????????100010001111
-`define VSSEGSTB 32'b????????????????????100000001111
-`define VFSSEGSTD 32'b????????????????????110110001111
-`define VFSSEGSTW 32'b????????????????????110100001111
-`define VMVV 32'b??????????0000000000000001110011
-`define VMSV 32'b??????????0000000000100001110011
-`define VMST 32'b???????????????00001000001110011
-`define VMTS 32'b???????????????00001100001110011
-`define VFMVV 32'b??????????0000000000000101110011
-`define VFMSV 32'b??????????0000000000100101110011
-`define VFMST 32'b???????????????00001000101110011
-`define VFMTS 32'b???????????????00001100101110011
-`define VVCFG 32'b00000??????????00000010001110011
-`define VTCFG 32'b00000??????????00000110001110011
-`define VVCFGIVL 32'b??????????????????????0011110011
-`define VTCFGIVL 32'b??????????????????????0111110011
-`define VSETVL 32'b??????????0000000000001011110011
-`define VF 32'b00000?????????????????1111110011
-`define C_LI 32'b???????????????????????????00000
-`define C_ADDI 32'b???????????????????????????00001
-`define C_ADDIW 32'b???????????????????????????11101
-`define C_LDSP 32'b???????????????????????????00100
-`define C_LWSP 32'b???????????????????????????00101
-`define C_SDSP 32'b???????????????????????????00110
-`define C_SWSP 32'b???????????????????????????01000
-`define C_LW0 32'b????????????????0??????????10010
-`define C_LD0 32'b????????????????1??????????10010
-`define C_ADD 32'b????????????????0??????????11010
-`define C_SUB 32'b????????????????1??????????11010
-`define C_MOVE 32'b????????????????0??????????00010
-`define C_J 32'b????????????????1??????????00010
-`define C_LD 32'b???????????????????????????01001
-`define C_LW 32'b???????????????????????????01010
-`define C_SD 32'b???????????????????????????01100
-`define C_SW 32'b???????????????????????????01101
-`define C_BEQ 32'b???????????????????????????10000
-`define C_BNE 32'b???????????????????????????10001
-`define C_FLW 32'b???????????????????????????10100
-`define C_FLD 32'b???????????????????????????10101
-`define C_FSW 32'b???????????????????????????10110
-`define C_FSD 32'b???????????????????????????11000
-`define C_SLLI 32'b???????????????????000?????11001
-`define C_SLLI32 32'b???????????????????001?????11001
-`define C_SRLI 32'b???????????????????010?????11001
-`define C_SRLI32 32'b???????????????????011?????11001
-`define C_SRAI 32'b???????????????????100?????11001
-`define C_SRAI32 32'b???????????????????101?????11001
-`define C_SLLIW 32'b???????????????????110?????11001
-`define C_ADD3 32'b??????????????????????00???11100
-`define C_SUB3 32'b??????????????????????01???11100
-`define C_OR3 32'b??????????????????????10???11100
-`define C_AND3 32'b??????????????????????11???11100
diff --git a/instr-table.tex b/instr-table.tex
index b6375da..6c4c84b 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -1309,7 +1309,7 @@
\multicolumn{1}{c|}{00000} &
\multicolumn{4}{c|}{1111000} &
\multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & MXTF.S rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FMV.S.X rd,rs1 \\
\cline{2-11}
@@ -1351,7 +1351,7 @@
\multicolumn{1}{c|}{00000} &
\multicolumn{4}{c|}{1110000} &
\multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & MFTX.S rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FMV.X.S rd,rs1 \\
\cline{2-11}
@@ -1798,7 +1798,7 @@
\multicolumn{1}{c|}{00000} &
\multicolumn{4}{c|}{1111000} &
\multicolumn{2}{c|}{001} &
-\multicolumn{1}{c|}{1010011} & MXTF.D rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FMV.D.X rd,rs1 \\
\cline{2-11}
@@ -1830,7 +1830,7 @@
\multicolumn{1}{c|}{00000} &
\multicolumn{4}{c|}{1110000} &
\multicolumn{2}{c|}{001} &
-\multicolumn{1}{c|}{1010011} & MFTX.D rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FMV.X.D rd,rs1 \\
\cline{2-11}
diff --git a/opcodes b/opcodes
index 6f3ea29..036dd83 100644
--- a/opcodes
+++ b/opcodes
@@ -183,11 +183,11 @@ fmax.s rd rs1 rs2 16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3
fmin.d rd rs1 rs2 16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3
fmax.d rd rs1 rs2 16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3
-mftx.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3
-mftx.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3
+fmv.x.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3
+fmv.x.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3
mffsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3
-mxtf.s rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3
-mxtf.d rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3
+fmv.s.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3
+fmv.d.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3
mtfsr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3
flw rd rs1 imm12 9..7=2 6..2=0x01 1..0=3
@@ -205,189 +205,3 @@ fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3
fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3
fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3
fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3
-
-# vector scalar instructions
-stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3
-utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3
-movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3
-movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3
-fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3
-fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3
-
-vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3
-vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3
-vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3
-
-vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3
-vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3
-venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3
-venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3
-venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3
-venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3
-
-# vector load mem instructions
-
-# 3=d
-# 2=seg 2=w
-# 1=st 1=seg 1=f 1=s 1=h
-# 0=u 0=etc 0=x 0=u 0=b
-# ----------------------------------------------------------------------------
-# mem padding type seg x/f u/s width opcode
-# unit stride | | | | | | | |
-# xloads | | | | | | | |
-vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
-
-# mem padding type seg x/f u/s width opcode
-# stride | | | | | | | |
-# xloads | | | | | | | |
-vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
-
-# mem padding type seg x/f u/s width opcode
-# segment | | | | | | | |
-# xloads | | | | | | | |
-vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
-
-# seg x/f u/s width opcode
-# stride segment | | | | |
-# xloads | | | | |
-vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3
-
-# vector store mem instructions
-# mem padding type seg x/f u/s width opcode
-# unit stride | | | | | | | |
-# xstores | | | | | | | |
-vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
-
-# mem padding type seg x/f u/s width opcode
-# stride | | | | | | | |
-# xstores | | | | | | | |
-vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
-
-# mem padding type seg x/f u/s width opcode
-# segment | | | | | | | |
-# xstores | | | | | | | |
-vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
-
-# seg x/f u/s width opcode
-# stride segment | | | | |
-# xstores | | | | |
-vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3
-
-# other vector register instructions
-vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3
-vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3
-vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3
-vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3
-vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3
-vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3
-vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3
-vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3
-vvcfg 31..27=0 rs1 rs2 16..11=0 10..8=4 7=0 6..2=0x1C 1..0=3
-vtcfg 31..27=0 rs1 rs2 16..11=1 10..8=4 7=0 6..2=0x1C 1..0=3
-
-# other vector immediate instructions
-vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3
-vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3
-vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3
-vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3
-
-# compressed instructions
-c.li cimm6 crd 4..0=0
-c.addi cimm6 crd 4..0=1
-c.addiw cimm6 crd 4..0=29
-c.ldsp cimm6 crd 4..0=4
-c.lwsp cimm6 crd 4..0=5
-c.sdsp cimm6 crd 4..0=6
-c.swsp cimm6 crd 4..0=8
-
-c.lw0 15=0 crs1 crd 4..0=18
-c.ld0 15=1 crs1 crd 4..0=18
-c.add 15=0 crs1 crd 4..0=26
-c.sub 15=1 crs1 crd 4..0=26
-c.move 15=0 crs1 crd 4..0=2
-
-c.j 15=1 cimm10 4..0=2
-
-c.ld crds crs1s cimm5 4..0=9
-c.lw crds crs1s cimm5 4..0=10
-c.sd crs2s crs1s cimm5 4..0=12
-c.sw crs2s crs1s cimm5 4..0=13
-c.beq crs2s crs1s cimm5 4..0=16
-c.bne crs2s crs1s cimm5 4..0=17
-c.flw crds crs1s cimm5 4..0=20
-c.fld crds crs1s cimm5 4..0=21
-c.fsw crs2s crs1s cimm5 4..0=22
-c.fsd crs2s crs1s cimm5 4..0=24
-
-c.slli crds 12..10=0 cimm5 4..0=25
-c.slli32 crds 12..10=1 cimm5 4..0=25
-c.srli crds 12..10=2 cimm5 4..0=25
-c.srli32 crds 12..10=3 cimm5 4..0=25
-c.srai crds 12..10=4 cimm5 4..0=25
-c.srai32 crds 12..10=5 cimm5 4..0=25
-c.slliw crds 12..10=6 cimm5 4..0=25
-
-c.add3 crds crs1s 9..8=0 crs2bs 4..0=28
-c.sub3 crds crs1s 9..8=1 crs2bs 4..0=28
-c.or3 crds crs1s 9..8=2 crs2bs 4..0=28
-c.and3 crds crs1s 9..8=3 crs2bs 4..0=28
diff --git a/opcodes-hwacha b/opcodes-hwacha
new file mode 100644
index 0000000..337523d
--- /dev/null
+++ b/opcodes-hwacha
@@ -0,0 +1,144 @@
+# vector scalar instructions
+stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3
+utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3
+movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3
+movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3
+fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3
+fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3
+
+vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3
+vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3
+vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3
+
+vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3
+vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3
+venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3
+venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3
+venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3
+venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3
+
+# vector load mem instructions
+
+# 3=d
+# 2=seg 2=w
+# 1=st 1=seg 1=f 1=s 1=h
+# 0=u 0=etc 0=x 0=u 0=b
+# ----------------------------------------------------------------------------
+# mem padding type seg x/f u/s width opcode
+# unit stride | | | | | | | |
+# xloads | | | | | | | |
+vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+# mem padding type seg x/f u/s width opcode
+# stride | | | | | | | |
+# xloads | | | | | | | |
+vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+# mem padding type seg x/f u/s width opcode
+# segment | | | | | | | |
+# xloads | | | | | | | |
+vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+# seg x/f u/s width opcode
+# stride segment | | | | |
+# xloads | | | | |
+vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3
+vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3
+vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3
+vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3
+vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3
+vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3
+vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3
+# floads
+vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3
+vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+
+# vector store mem instructions
+# mem padding type seg x/f u/s width opcode
+# unit stride | | | | | | | |
+# xstores | | | | | | | |
+vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+# mem padding type seg x/f u/s width opcode
+# stride | | | | | | | |
+# xstores | | | | | | | |
+vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+# mem padding type seg x/f u/s width opcode
+# segment | | | | | | | |
+# xstores | | | | | | | |
+vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+# seg x/f u/s width opcode
+# stride segment | | | | |
+# xstores | | | | |
+vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3
+vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3
+vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3
+vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3
+# fstores
+vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3
+vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+
+# other vector register instructions
+vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3
+vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3
+vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3
+vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3
+vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3
+vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3
+vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3
+vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3
+vvcfg 31..27=0 rs1 rs2 16..11=0 10..8=4 7=0 6..2=0x1C 1..0=3
+vtcfg 31..27=0 rs1 rs2 16..11=1 10..8=4 7=0 6..2=0x1C 1..0=3
+
+# other vector immediate instructions
+vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3
+vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3
+vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3
+vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3
diff --git a/opcodes-rvc b/opcodes-rvc
new file mode 100644
index 0000000..98f5b99
--- /dev/null
+++ b/opcodes-rvc
@@ -0,0 +1,40 @@
+# compressed instructions
+c.li cimm6 crd 4..0=0
+c.addi cimm6 crd 4..0=1
+c.addiw cimm6 crd 4..0=29
+c.ldsp cimm6 crd 4..0=4
+c.lwsp cimm6 crd 4..0=5
+c.sdsp cimm6 crd 4..0=6
+c.swsp cimm6 crd 4..0=8
+
+c.lw0 15=0 crs1 crd 4..0=18
+c.ld0 15=1 crs1 crd 4..0=18
+c.add 15=0 crs1 crd 4..0=26
+c.sub 15=1 crs1 crd 4..0=26
+c.move 15=0 crs1 crd 4..0=2
+
+c.j 15=1 cimm10 4..0=2
+
+c.ld crds crs1s cimm5 4..0=9
+c.lw crds crs1s cimm5 4..0=10
+c.sd crs2s crs1s cimm5 4..0=12
+c.sw crs2s crs1s cimm5 4..0=13
+c.beq crs2s crs1s cimm5 4..0=16
+c.bne crs2s crs1s cimm5 4..0=17
+c.flw crds crs1s cimm5 4..0=20
+c.fld crds crs1s cimm5 4..0=21
+c.fsw crs2s crs1s cimm5 4..0=22
+c.fsd crs2s crs1s cimm5 4..0=24
+
+c.slli crds 12..10=0 cimm5 4..0=25
+c.slli32 crds 12..10=1 cimm5 4..0=25
+c.srli crds 12..10=2 cimm5 4..0=25
+c.srli32 crds 12..10=3 cimm5 4..0=25
+c.srai crds 12..10=4 cimm5 4..0=25
+c.srai32 crds 12..10=5 cimm5 4..0=25
+c.slliw crds 12..10=6 cimm5 4..0=25
+
+c.add3 crds crs1s 9..8=0 crs2bs 4..0=28
+c.sub3 crds crs1s 9..8=1 crs2bs 4..0=28
+c.or3 crds crs1s 9..8=2 crs2bs 4..0=28
+c.and3 crds crs1s 9..8=3 crs2bs 4..0=28
diff --git a/parse-opcodes b/parse-opcodes
index 19a8bb9..8c1c771 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -469,8 +469,8 @@ def make_latex_table():
print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s', 'fmin.s', 'fmax.s')
print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s')
print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s')
- print_insts('fcvt.s.w', 'fcvt.s.wu', 'mxtf.s', 'mtfsr')
- print_insts('fcvt.w.s', 'fcvt.wu.s', 'mftx.s', 'mffsr')
+ print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x', 'mtfsr')
+ print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s', 'mffsr')
print_insts('feq.s', 'flt.s', 'fle.s')
print_footer(0)
@@ -487,8 +487,8 @@ def make_latex_table():
print_insts('fcvt.w.d', 'fcvt.wu.d')
print_insts('feq.d', 'flt.d', 'fle.d')
print_subtitle('RV64D Instruction Subset')
- print_insts('fcvt.d.l', 'fcvt.d.lu', 'mxtf.d')
- print_insts('fcvt.l.d', 'fcvt.lu.d', 'mftx.d')
+ print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x')
+ print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d')
print_insts('fcvt.s.d', 'fcvt.d.s')
print_footer(1)
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-09 02:28:33 +0000