diff options
| author |  Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-25 01:43:47 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-25 01:43:47 -0800 |
| commit | 2d11bac94537e08b30b8ace0eb39ecbbbc386c8e (patch) | |
| tree | 5c9b9dcee1a2fe0e2fb666020d552a207daa8958 /opcodes | |
| parent | bc445390566f8831dd8bb34bcc05d80c7401296a (diff) | |
New privileged ISA
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes | 71 |
1 files changed, 35 insertions, 36 deletions
@@ -42,15 +42,6 @@ sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 -mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 -mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 -mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 -mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 -div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 -divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 -rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 -remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 - addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 @@ -62,12 +53,6 @@ sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 -mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 -divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 -divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 -remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 -remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 - lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 @@ -81,6 +66,27 @@ sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 +fence 31..28=ignore pred succ 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 +fence.i 31..28=ignore 27..20=ignore 19..15=ignore 14..12=1 11..7=ignore 6..2=0x03 1..0=3 + +# RV32M +mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 +mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 + +# RV64M +mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 +divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 +divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 +remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 +remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 + +# RV32A amoadd.w rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 amoxor.w rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 amoor.w rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 @@ -92,7 +98,8 @@ amomaxu.w rd rs1 rs2 aqrl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 amoswap.w rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 lr.w rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 sc.w rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 - + +# RV64A amoadd.d rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 amoxor.d rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 amoor.d rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 @@ -105,24 +112,18 @@ amoswap.d rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 lr.d rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 -fence 31..28=ignore pred succ 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 -fence.i 31..28=ignore 27..20=ignore 19..15=ignore 14..12=1 11..7=ignore 6..2=0x03 1..0=3 - -syscall 11..7=0 19..15=0 24..20=0 31..25=0 14..12=0 6..2=0x1D 1..0=3 -break 11..7=0 19..15=0 24..20=0 31..25=0 14..12=1 6..2=0x1D 1..0=3 -rdcycle rd 19..15=0 24..20=0 31..25=0 14..12=4 6..2=0x1D 1..0=3 -rdtime rd 19..15=0 24..20=0 31..25=1 14..12=4 6..2=0x1D 1..0=3 -rdinstret rd 19..15=0 24..20=0 31..25=2 14..12=4 6..2=0x1D 1..0=3 - -# SUPERVISOR -mtpcr rd rs1 rs2 31..25=0 14..12=0 6..2=0x1C 1..0=3 -mfpcr rd rs1 24..20=0 31..25=0 14..12=1 6..2=0x1C 1..0=3 -setpcr rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 -clearpcr rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 -eret 11..7=0 19..15=0 24..20=0 31..25=0 14..12=4 6..2=0x1C 1..0=3 - -# 0x7C-0x7F are reserved for >32b instructions - +# SYSTEM +scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 +sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x800 14..12=0 6..2=0x1C 1..0=3 +csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 +csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 + +# F/D EXTENSIONS fadd.s rd rs1 rs2 31..27=0x0 rm 26..25=0 6..2=0x14 1..0=3 fsub.s rd rs1 rs2 31..27=0x1 rm 26..25=0 6..2=0x14 1..0=3 fmul.s rd rs1 rs2 31..27=0x2 rm 26..25=0 6..2=0x14 1..0=3 @@ -180,10 +181,8 @@ fmax.d rd rs1 rs2 31..27=0x19 14..12=0 26..25=1 6..2=0x14 1..0=3 fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 -frsr rd 19..15=0 24..20=0 31..27=0x1D 14..12=0 26..25=0 6..2=0x14 1..0=3 fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 -fssr rd rs1 24..20=0 31..27=0x1F 14..12=0 26..25=0 6..2=0x14 1..0=3 flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 |