remove hwachaV3 definitions

4 files changed, 1 insertions, 194 deletions

diff --git a/Makefile b/Makefile
index 906c411..0fa58a0 100644
--- a/Makefile
+++ b/Makefile
@@ -1,13 +1,12 @@
 SHELL := /bin/sh
 
 ISASIM_H := ../riscv-isa-sim/riscv/encoding.h
-ISASIM_HWACHA_H := ../riscv-isa-sim/hwacha/opcodes_hwacha_ut.h
 PK_H := ../riscv-pk/pk/encoding.h
 FESVR_H := ../riscv-fesvr/fesvr/encoding.h
 ENV_H := ../riscv-tests/env/encoding.h
 GAS_H := ../riscv-gnu-toolchain/binutils/include/opcode/riscv-opc.h
 
-ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-hwacha-pseudo opcodes-hwacha opcodes-hwacha-ut opcodes-custom
+ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom
 
 install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) inst.chisel instr-table.tex priv-instr-table.tex
 
@@ -18,11 +17,6 @@ $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes encoding.h
 $(GAS_H) $(XCC_H): $(ALL_OPCODES) parse-opcodes
 	cat $(ALL_OPCODES) | ./parse-opcodes -c > $@
 
-$(ISASIM_HWACHA_H): $(ALL_OPCODES) parse-opcodes
-	cat opcodes opcodes-hwacha-ut | ./parse-opcodes -c | \
-	sed 's/DECLARE_INSN(/DECLARE_INSN(ut_/g' | \
-	cpp -P -D DECLARE_INSN=DECLARE_INSN | sort -o $@
-
 inst.chisel: $(ALL_OPCODES) parse-opcodes
 	cat opcodes opcodes-custom opcodes-pseudo | ./parse-opcodes -chisel > $@
 
diff --git a/opcodes-hwacha b/opcodes-hwacha
deleted file mode 100644
index 3d3d33d..0000000
--- a/opcodes-hwacha
+++ /dev/null
@@ -1,78 +0,0 @@
-# rocc format, xd = inst[14], xs1 = inst[13], xs2 = inst[12]
-
-# vector instructions
-vsetcfg      imm12             rs1      14=0 13=1 12=0 11..7=0 6..2=0x02 1..0=3
-vsetvl       31..25=0 24..20=0 rs1      14=1 13=1 12=0 rd      6..2=0x02 1..0=3
-vgetcfg      31..25=0 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x02 1..0=3
-vgetvl       31..25=1 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x02 1..0=3
-
-vmvv         31..25=1 24..20=0 rs1      14=0 13=0 12=0 rd      6..2=0x0A 1..0=3
-vmsv         31..25=1 24..20=0 rs1      14=0 13=1 12=0 rd      6..2=0x0A 1..0=3
-vfmvv        31..25=9 24..20=0 rs1      14=0 13=0 12=0 rd      6..2=0x0A 1..0=3
-vfmvv        31..25=8 24..20=0 rs1      14=0 13=0 12=0 rd      6..2=0x0A 1..0=3
-vfmsv.s      31..25=8 24..20=0 rs1      14=0 13=1 12=0 rd      6..2=0x0A 1..0=3
-vfmsv.d      31..25=9 24..20=0 rs1      14=0 13=1 12=0 rd      6..2=0x0A 1..0=3
-
-vf           imm12hi  24..20=1 rs1      14=0 13=1 12=0 imm12lo 6..2=0x0A 1..0=3
-
-# vector supervisor instructions
-vxcptcause   31..25=0 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x0A 1..0=3
-vxcptaux     31..25=1 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x0A 1..0=3
-
-vxcptsave    31..25=0 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-vxcptrestore 31..25=1 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-vxcptkill    31..25=2 24..20=0 19..15=0 14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-
-vxcptevac    31..25=3 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-vxcpthold    31..25=4 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-venqcmd      31..25=5 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-venqimm1     31..25=6 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-venqimm2     31..25=7 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-venqcnt      31..25=8 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x0A 1..0=3
-
-#                              3=d
-#                              2=w
-#                    1=f  1=u  1=h                   0    1    1=strided
-#           3-bits   0=x  0=s  0=b                   0    1    0=unit-strided
-#           ---------------------------------------------------------------------------
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-vlsegd      vseglen  28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlsegw      vseglen  28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlsegwu     vseglen  28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlsegh      vseglen  28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlseghu     vseglen  28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlsegb      vseglen  28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlsegbu     vseglen  28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vflsegd     vseglen  28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vflsegw     vseglen  28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-vlsegstd    vseglen  28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsegstw    vseglen  28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsegstwu   vseglen  28=0 27=1 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsegsth    vseglen  28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsegsthu   vseglen  28=0 27=1 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsegstb    vseglen  28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsegstbu   vseglen  28=0 27=1 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vflsegstd   vseglen  28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vflsegstw   vseglen  28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-vssegd      vseglen  28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vssegw      vseglen  28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vssegh      vseglen  28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vssegb      vseglen  28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vfssegd     vseglen  28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vfssegw     vseglen  28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-vssegstd    vseglen  28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vssegstw    vseglen  28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vssegsth    vseglen  28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vssegstb    vseglen  28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vfssegstd   vseglen  28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vfssegstw   vseglen  28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
diff --git a/opcodes-hwacha-pseudo b/opcodes-hwacha-pseudo
deleted file mode 100644
index 06466c7..0000000
--- a/opcodes-hwacha-pseudo
+++ /dev/null
@@ -1,46 +0,0 @@
-#                              3=d
-#                              2=w
-#                    1=f  1=u  1=h                   0    1    1=strided
-#           3-bits   0=x  0=s  0=b                   0    1    0=unit-strided
-#           ---------------------------------------------------------------------------
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-@vld         31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vlw         31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vlwu        31..29=0 28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vlh         31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vlhu        31..29=0 28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vlb         31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vlbu        31..29=0 28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vfld        31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-@vflw        31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-@vlstd       31..29=0 28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vlstw       31..29=0 28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vlstwu      31..29=0 28=0 27=1 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vlsth       31..29=0 28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vlsthu      31..29=0 28=0 27=1 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vlstb       31..29=0 28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vlstbu      31..29=0 28=0 27=1 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vflstd      31..29=0 28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-@vflstw      31..29=0 28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-@vsd         31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-@vsw         31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-@vsh         31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-@vsb         31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-@vfsd        31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-@vfsw        31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-
-#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
-#           |        |    |    |                     |    |    |       |
-@vsstd       31..29=0 28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-@vsstw       31..29=0 28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-@vssth       31..29=0 28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-@vsstb       31..29=0 28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-@vfsstd      31..29=0 28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-@vfsstw      31..29=0 28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
diff --git a/opcodes-hwacha-ut b/opcodes-hwacha-ut
deleted file mode 100644
index eeb6937..0000000
--- a/opcodes-hwacha-ut
+++ /dev/null
@@ -1,63 +0,0 @@
-# format of a line in this file:
-# <instruction name> <args> <opcode>
-#
-# <opcode> is given by specifying one or more range/value pairs:
-# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
-#
-# <args> is one of rd, rs1, rs2, rs3, imm25, imm20, imm12, imm12lo, imm12hi,
-# shamtw, shamt, rm
-
-# vector scalar instructions
-stop    31..25=0 24..20=0 19..15=0 14..12=5 11..7=0 6..2=0x1D 1..0=3
-utidx   31..25=0 24..20=0 19..15=0 14..12=6 rd      6..2=0x1D 1..0=3
-movz    31..25=0 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
-movn    31..25=1 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
-fmovz   31..25=2 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
-fmovn   31..25=3 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
-
-# half-precision floating-point operations for hwacha microthreads
-
-fadd.h      rd rs1 rs2      31..27=0x0  rm       26..25=2 6..2=0x14 1..0=3
-fsub.h      rd rs1 rs2      31..27=0x1  rm       26..25=2 6..2=0x14 1..0=3
-fmul.h      rd rs1 rs2      31..27=0x2  rm       26..25=2 6..2=0x14 1..0=3
-fdiv.h      rd rs1 rs2      31..27=0x3  rm       26..25=2 6..2=0x14 1..0=3
-fsqrt.h     rd rs1 24..20=0 31..27=0x4  rm       26..25=2 6..2=0x14 1..0=3
-fsgnj.h     rd rs1 rs2      31..27=0x5  14..12=0 26..25=2 6..2=0x14 1..0=3
-fsgnjn.h    rd rs1 rs2      31..27=0x6  14..12=0 26..25=2 6..2=0x14 1..0=3
-fsgnjx.h    rd rs1 rs2      31..27=0x7  14..12=0 26..25=2 6..2=0x14 1..0=3
-
-fcvt.h.l    rd rs1 24..20=0 31..27=0xC  rm      26..25=2 6..2=0x14 1..0=3
-fcvt.h.lu   rd rs1 24..20=0 31..27=0xD  rm      26..25=2 6..2=0x14 1..0=3
-fcvt.h.w    rd rs1 24..20=0 31..27=0xE  rm      26..25=2 6..2=0x14 1..0=3
-fcvt.h.wu   rd rs1 24..20=0 31..27=0xF  rm      26..25=2 6..2=0x14 1..0=3
-
-fcvt.l.h    rd rs1 24..20=0 31..27=0x8  rm      26..25=2 6..2=0x14 1..0=3
-fcvt.lu.h   rd rs1 24..20=0 31..27=0x9  rm      26..25=2 6..2=0x14 1..0=3
-fcvt.w.h    rd rs1 24..20=0 31..27=0xA  rm      26..25=2 6..2=0x14 1..0=3
-fcvt.wu.h   rd rs1 24..20=0 31..27=0xB  rm      26..25=2 6..2=0x14 1..0=3
-
-fcvt.s.h    rd rs1 24..20=0 31..29=0x4 28..27=0 rm 26..25=2 6..2=0x14 1..0=3
-fcvt.h.s    rd rs1 24..20=0 31..29=0x4 28..27=2 rm 26..25=0 6..2=0x14 1..0=3
-
-fcvt.d.h    rd rs1 24..20=0 31..29=0x4 28..27=1 rm 26..25=2 6..2=0x14 1..0=3
-fcvt.h.d    rd rs1 24..20=0 31..29=0x4 28..27=2 rm 26..25=1 6..2=0x14 1..0=3
-
-feq.h     rd rs1 rs2      31..27=0x15 14..12=0 26..25=2 6..2=0x14 1..0=3
-flt.h     rd rs1 rs2      31..27=0x16 14..12=0 26..25=2 6..2=0x14 1..0=3
-fle.h     rd rs1 rs2      31..27=0x17 14..12=0 26..25=2 6..2=0x14 1..0=3
-
-fmin.h    rd rs1 rs2      31..27=0x18 14..12=0 26..25=2 6..2=0x14 1..0=3
-fmax.h    rd rs1 rs2      31..27=0x19 14..12=0 26..25=2 6..2=0x14 1..0=3
-
-fmv.x.h     rd rs1      24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3
-fmv.h.x     rd rs1      24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3
-
-flh        rd rs1 imm12 14..12=1 6..2=0x01 1..0=3
-
-fsh        imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3
-
-fmadd.h     rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3
-fmsub.h     rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3
-fnmsub.h    rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3
-fnmadd.h    rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3
-