diff options
Diffstat (limited to 'SrcShared/Palm/Device/EZAustin')
| -rw-r--r-- | SrcShared/Palm/Device/EZAustin/IncsPrv/HardwareAustin.h | 214 | ||||
| -rw-r--r-- | SrcShared/Palm/Device/EZAustin/IncsPrv/SED1375Hwr.h | 240 |
2 files changed, 454 insertions, 0 deletions
diff --git a/SrcShared/Palm/Device/EZAustin/IncsPrv/HardwareAustin.h b/SrcShared/Palm/Device/EZAustin/IncsPrv/HardwareAustin.h new file mode 100644 index 0000000..f08fe36 --- /dev/null +++ b/SrcShared/Palm/Device/EZAustin/IncsPrv/HardwareAustin.h @@ -0,0 +1,214 @@ +/****************************************************************************** + * + * Copyright (c) 1995-1999 Palm Computing, Inc. or its subsidiaries. + * All rights reserved. + * + * File: HardwareAustin.h + * + * Description: + * Hardware Equates for the EZ (Austin) platform. This header file + * contains equates specific to Hardware platform EZ. + * + * History: + * 03/04/99 ben Created from HardwareEZ.h + * 07/15/99 kwk Added hwrDigitizerWidth & hwrDigitizerHeight. + * + *****************************************************************************/ + +#ifdef NON_PORTABLE // So app's don't mistakenly include this + +#ifndef __HARDWAREAUSTIN_H__ +#define __HARDWAREAUSTIN_H__ + + +/*********************************************************************** + * EZ Rev of the Pilot Hardware + ***********************************************************************/ +#define hwr68328Base 0xFFFFF000L // Base address of 68328 + +// Define the base of card 0 and the size of each card slot. +#define hwrCardBase0 0x00000000L // starts here (just above Dheap) +#define hwrCardSize 0x20000000L // Size of each card slot +#define hwrFlashBase 0x10C00000L // Base of Flash ROM +//#define hwrFlashSize 0x00400000L // Size of Flash ROM +#define hwrCardOffsetMask 0x1FFFFFFFL // Used to convert a pointer to a card offset +#define hwrMinBigROMOffset 0x00008000L // Minimum ROM offset to BigROM + + +// Define the Flash width +#define hwrROMWidth 2 + + +/************************************************************************ + * Port B Bit settings + ************************************************************************/ +#define hwrEZPortBLCD_CS 0x01 // (L) LCD Chip Select +#define hwrEZPortBCS_ADC 0x02 // (L) BurrBrown Chip-select +#define hwrEZPortBLCDBright 0x08 // (L) LCD Brightness controller SYNC +#define hwrEZPortBRS232Enable 0x40 // (H) Enable the RS232 Transceiver +#define hwrEZPortBSoundUnfiltered 0x80 // (-) Unfiltered Sound + + +/************************************************************************ + * Port C Bit settings + ************************************************************************/ +#define hwrEZPortCKbdRow0 0x01 // (H) Keyboard Row 0 +#define hwrEZPortCKbdRow1 0x02 // (H) Keyboard Row 1 +#define hwrEZPortCKbdRow2 0x04 // (H) Keyboard Row 2 +#define hwrEZPortCCharging 0x08 // (L) Battery Charging - Low if battery is charging. +#define hwrEZPortCKbdRows 0x07 // All Keyboard Rows + +#define hwrEZPortCBacklightEnable 0x10 // (H) Enable SED1375 Backlight +#define hwrEZPortCChargerShutdown 0x20 // (H) Output high to disable the charger +#define hwrEZPortCEnable5V 0x40 // (H) Enable 5V power supply for screen +#define hwrEZPortCEnableDTR 0x80 // (H) Assert Serial DTR signal. + + +/************************************************************************ + * Port D Bit settings + ************************************************************************/ + +#define hwrEZPortDKbdCol0 0x01 // (H) Keyboard Column 0 (aka INT0) +#define hwrEZPortDKbdCol1 0x02 // (H) Keyboard Column 1 (aka INT1) +#define hwrEZPortDKbdCol2 0x04 // (H) Keyboard Column 2 (aka INT2) +#define hwrEZPortDKbdCol3 0x08 // (H) Keyboard Column 3 (aka INT3) +#define hwrEZPortDKeyBits 0x0F // All Keyboard Columns + +#define hwrEZPortDDockButton 0x10 // (L) IRQ1 HotSync/Dock Button +#define hwrEZPortDGoodBattery 0x20 // (H) IRQ2 Good Battery +#define hwrEZPortDAdapterInstalled 0x40 // (L) IRQ3 Adapter installed +#define hwrEZPortDPowerFail 0x80 // (L) Power Fail interrupt (IRQ6) + + +// DANGER: Writing to PortD to (for example) toggle the serial enable bit has potential side effects. +// For example, if we |= or &= the serial enable bit (as PrvSerialEnable used to do) and inadvertently +// write other one-bits to portDData, we may clear pending edge interrupts on those other bits, like +// for example, the keyboard edge interrupt bits. Though the docs are somewhat ambiguous (surprise!), +// it would APPEAR that this is only the case for the keyboard interrupt bits (INT0-INT3). This DID +// cause problems when re-enabling the serial port during HwrWake->SerialWake, as it would clear any +// pending keyboard interrupts that woke the device (such as the power key or application buttons). +// SO, when writing to the serial enable bit, we MUST be sure to mask against hwrEZPortDDataMaskBeforeWrite +// before writing to portDData. This is ALSO VERY IMPORTANT for anyone who might make use of bit 6 (IRQ3) +// as an output pin. Whenever writing to hwrEZPortDFree3, one should always read portDData first, twiddle +// hwrEZPortDFree3 as appropriate, and with hwrEZPortDDataMaskBeforeWrite and finally write to portDData. +// Maybe in future parts, Moto can spare us a PortDIntStatus register, separate from portDData. + +#define hwrEZPortDDataMaskBeforeWrite (~(hwrEZPortDKeyBits)) // Don't write ones to these bits! + +#define hwrEZPortDKeyOffset 0x0 // bits to shift to put Col 0 in lsb + +/************************************************************************ + * Port E Bit settings + ************************************************************************/ +#define hwrEZPortESpiTxD 0x01 // (L) SPI TXD (Internal) +#define hwrEZPortESpiRxD 0x02 // (L) SPI RXD (Internal) +#define hwrEZPortESpiClk 0x04 // SPI Clock +#define hwrEZPortESpiBits 0x07 // all the SPI bits +#define hwrEZPortERXD 0x10 // external RXD +#define hwrEZPortETXD 0x20 // external TXD +#define hwrEZPortERTS 0x40 // external RTS +#define hwrEZPortECTS 0x80 // external CTS + + +/************************************************************************ + * Port F Bit settings + ************************************************************************/ + +#define hwrEZPortFLCDPowered 0x01 // (H) Input asserted when LCD is at full power. +#define hwrEZPortFPenIO 0x02 // (H) Pen Interrupt, Pen IO (IRQ5) +#define hwrEZPortFBusClock 0x04 // (H) Bus Clock +#define hwrEZPortFA20 0x08 // (H) A20 + +#define hwrEZPortFA21 0x10 // (H) A21 +#define hwrEZPortFVideoClkEnable 0x20 // (H) Enable Video clock. +#define hwrEZPortFBatteryEnable 0x40 // (H) Battery Enable +#define hwrEZPortFIXTRNL2 0x80 // (L) IXTRNL2 line, used to ID the device connected to the sync port. + + +/************************************************************************ + * Port G Bit settings + ************************************************************************/ + +#define hwrEZPortGDTACK 0x01 // (-) DTACK +#define hwrEZPortGA0 0x02 // (-) A0 +#define hwrEZPortGIDDetect 0x04 // (L) ID select (drives kbd) +#define hwrEZPortGHiZ 0x08 // (L) Used in ICT to tristate dragonball pins +#define hwrEZPortGIRShutdown 0x10 // (H) Shutdown IRDA +#define hwrEZPortGEmuBrk 0x20 // (-) EMUBRK + + +/************************************************************************ + * SPIM Base Configuration + ************************************************************************/ +#define hwrEZSPIMBaseControl (hwrEZ328SPIMControlRateDiv16 | \ + hwrEZ328SPIMControlIntEnable | \ + hwrEZ328SPIMControlInvPolarity | \ + hwrEZ328SPIMControlOppPhase | \ + 16-1) + + + +/************************************************************************ + *Initial values for the PLL. We set the system clock to be VCO/1 so + * the system clock speed becomes: + * + * 32768 * ((hwrEZFreqSelP + 1) * 14 + hwrEZFreqSelQ + 1) + * -------------------------------------------------------- + * VCO divider + ************************************************************************/ +// NEW ASIC versions run at 16.580608 Mhz + +#define hwrEZPLLControl (hwrEZ328PLLControlClkEn | \ + hwrEZ328PLLControlSysDMADiv1 | \ + hwrEZ328PLLControlPixDMADiv1 | \ + hwrEZ328PLLControlDMAVCODiv1) + + +// The Frequency needs to be lowered on the older DragonBall-EZ processors. +// +// The values are: +// 15MHz: Allows processor to operate without screen noise within the voltage +// range specified for the Power Supply (3.3V +- 100mV) +// P = 0x1F, Q=0x9 +// 13.5 MHz: Brings processor into voltage spec (runs as low as 3.0V without noise) +// P = 0x1C, Q=0x7 +// +// The following are the OK values for 0J83C processors (id 4) +// 16.580608 is the spec'd frequency for the part. HK admits that 20MHz works +// 16.580608MHz: P = 0x23, Q=0x01 +// 20.0 MHz: P = 0x2A, Q=0x9 + +#define hwrEZFreqSelPQ_13_5MHz (0x1C | (0x07 << 8)) + +#define hwrEZFreqSelPQ_14_75MHz (0x1F | (0x01 << 8)) + +#define hwrEZFreqSelPQ_15MHz (0x1F | (0x09 << 8)) + +#define hwrEZFreqSelPQ_16MHz (0x23 | (0x01 << 8)) + +#define hwrEZFreqSelPQ_20MHz (0x2A | (0x09 << 8)) + + +/************************************************************************ + * Display constants specific to Austin product. + ************************************************************************/ + +#define hwrDisplayBootDepth 8 // Boot time bits per pixel (system default) + +#define hwrDisplayWidth 160 // Physical Screen Width +#define hwrDisplayHeight 160 // Physical Screen Height +#define hwrDisplayMaxDepth 8 // Maximum bits per pixel hardware supports + +#define hwrDigitizerWidth hwrDisplayWidth // Same as width of display +#define hwrDigitizerHeight 220 // Height of digitizer area + +// Screen refresh rate +#define hwrDisplayPeriod 13 // frame period in ms. + +// Brightness Control Adjuster special values +#define hwrDisplayBrightAdjLowPwr 0x2000 // Sets special low power state for brightness adjust. + + +#endif // __HARDWAREAUSTIN_H__ + +#endif // NON_PORTABLE diff --git a/SrcShared/Palm/Device/EZAustin/IncsPrv/SED1375Hwr.h b/SrcShared/Palm/Device/EZAustin/IncsPrv/SED1375Hwr.h new file mode 100644 index 0000000..dc85e2a --- /dev/null +++ b/SrcShared/Palm/Device/EZAustin/IncsPrv/SED1375Hwr.h @@ -0,0 +1,240 @@ +/****************************************************************************** + * + * Copyright (c) 1998-1999 Palm Computing, Inc. or its subsidiaries. + * All rights reserved. + * + * File: SED1375Hwr.h + * + * Description: + * Hardware definitions for SED1375 controller. + * + * History: + * 12/14/98 BRM Adpated from SED1374 Test tool by Bob Ebert. + * + *****************************************************************************/ + +//----------------------------------------------------------------------- +// SED1375 Registers +//----------------------------------------------------------------------- + +typedef struct SED1375RegsType { + UInt8 productRevisionCode; // 0x00 + UInt8 mode0; // 0x01 + + UInt8 mode1; // 0x02 + UInt8 mode2; // 0x03 + + UInt8 horizontalPanelSize; // 0x04 + UInt8 verticalPanelSizeLSB; // 0x05 + + UInt8 verticalPanelSizeMSB; // 0x06 + UInt8 FPLineStartPosition; // 0x07 + + UInt8 horizontalNonDisplayPeriod; // 0x08 + UInt8 FPFRAMEStartPosition; // 0x09 + + UInt8 verticalNonDisplayPeriod; // 0x0A + UInt8 MODRate; // 0x0B + + UInt8 screen1StartAddressLSB; // 0x0C + UInt8 screen1StartAddressMSB; // 0x0D + + UInt8 screen2StartAddressLSB; // 0x0E + UInt8 screen2StartAddressMSB; // 0x0F + + UInt8 screen1StartAddressMSBit; // 0x10 !!! YES, screen1MSBit in a weird place. Send complaints to Epson. + UInt8 memoryAddressOffset; // 0x11 + + UInt8 screen1VerticalSizeLSB; // 0x12 + UInt8 screen1VerticalSizeMSB; // 0x13 + + UInt8 unused1; // 0x14 + UInt8 lookUpTableAddress; // 0x15 + + UInt8 unused2; // 0x16 + UInt8 lookUpTableData; // 0x17 + + UInt8 GPIOConfigurationControl; // 0x18 + UInt8 GPIOStatusControl; // 0x19 + + UInt8 scratchPad; // 0x1A + UInt8 portraitMode; // 0x1B + + UInt8 lineByteCountRegister; // 0x1C, for portrait mode only + UInt8 unused3; // 0x01D not used + + UInt8 unused4; // 0x1E + UInt8 unused5; // 0x1F +} SED1375RegsType; + +typedef volatile SED1375RegsType *SED1375RegsPtr; + + +//----------------------------------------------------------------------- +// Register constants and definitions +//----------------------------------------------------------------------- +#define sed1375BaseAddress 0x1F000000 +#define sed1375RegisterOffset 0x1FFE0 +#define sed1375RegsAddr ((UInt8 *)sed1375BaseAddress + sed1375RegisterOffset) + +#define sed1375VideoMemStart sed1375BaseAddress +#define sed1375VideoMemSize 81920 // 80K of memory for VRAM and CLUT's + + +// REG[0x00] Revision Code Register +// bits 7-2 are product code, bits 1-0 are revision code +#define sed1375RevisionCodeRegister 0x00 +#define sed1375ProductCodeMask 0xFC +#define sed1375RevisionCodeMask 0x03 +#define sed1375ProductCode 0x06 +#define sed1375ProductCodeExpected (sed1375ProductCode << 2) +#define sed1375RevisionCodeExpected 0x00 + +// REG[0x01] Mode Register 0 +// bits 6 (Dual/Single) and 5 (Color/Mono) and 1 (mode) are ignored if bit 7 is set. +#define sed1375ModeRegister0 0x01 +#define sed1375ModeTFT 0x80 // bit 7 +#define sed1375ModeDual 0x40 // bit 6 +#define sed1375ModeColor 0x20 // bit 5 +#define sed1375FPLineActiveHigh 0x10 // bit 4 +#define sed1375FPFramePolarityActiveHigh 0x07 // bit 3 +#define sed1375FPShiftMasked 0x04 // bit 2 +#define sed1375DataWidth12BitTFTPanel 0x01 // bits 1-0 + +// REG[0x02] Mode Register 1 +#define sed1375ModeRegister1 0x02 +#define sed1375BPPMask 0xC0 // bits 7,6 +#define sed1375BPPShift 6 +#define sed1375BPP(n) ((((n) - 1) & 0x04) << sed1375BPPShift) +#define sed13758bpp 0xC0 +#define sed13754bpp 0x80 +#define sed13752bpp 0x40 +#define sed13751bpp 0x00 +#define sed1375HighPerformance 0x20 // bit 5 +#define sed1375InputClockDiv2 0x10 // bit 4 +#define sed1375DisplayBlank 0x08 // bit 3 +#define sed1375FrameRepeat 0x04 // bit 2 +#define sed1375HardwareVideoInvertEnable 0x02 // bit 1 +#define sed1375SoftwareVideoInvert 0x01 // bit 0 + +// REG[0x03] Mode Register 2 +#define sed1375ModeRegister2 0x03 +#define sed1375LCDPWROverride 0x08 // bit 3 +#define sed1375HwrPowerSaveEnable 0x04 // bit 2 +#define sed1375PowerSaveMode 0x00 // bits 1,0 +#define sed1375PowerSaveNormalOperation 0x03 + +// REG[0x04] Horizontal Panel Size Register +// (Horizontal Panel Resolution pixels / 8)-1 +#define sed1375HorizontalPanelSizeRegister 0x04 +#define sed1375HorizontalResolutionMask 0x7F // bits 6-0 + +// REG[0x05] Vertical Panel Size Register (LSB) +// REG[0x06] Vertical Panel Size Register (MSB) +// together define 10 bits of vertical lines, set to # of lines - 1 +#define sed1375VerticalPanelSizeRegisterLSB 0x05 +#define sed1375VerticalPanelSizeRegisterMSB 0x06 +#define sed1375VerticalResolutionMSBMask 0x30 // bits 1,0 + +// REG[0x07] FPLINE Start Position +#define sed1375FPLINEStartPosition 0x07 +#define sed1375FPLINEStartPositionMask 0x1F // bits 4-0 + +// REG[0x08] Horizontal Non-Display Period +#define sed1375HorizontalNonDisplayPeriod 0x08 +#define sed1375HorizontalNonDisplayMask 0x1F // bits 4-0 +#define sed1375NoHorizontalNonDisplay 0x00 + +// REG[0x09] FPFRAME Start Position +#define sed1375FPFRAMEStartPosition 0x09 +#define sed1375FPFRAMEStartPositionMask 0x3F // bits 5-0 + +// REG[0x0A] Vertical Non-Display Period +#define sed1375VerticalNonDisplayPeriod 0x0A +#define sed1375VerticalNonDisplayStatus 0x80 // bit 7 +#define sed1375VerticalNonDisplayMask 0x3F // bits 5-0 +#define sed1375NoVerticalNonDisplay 0x00 + +// REG[0x0B] MOD Rate Register (passive LCD only) +#define sed1375MODRateRegister 0x0B +#define sed1375MODRateUnused 0x00 + +// REG[0x0C] Screen 1 Start Address Register (LSB) +// REG[0x0D] Screen 1 Start Address Register (MSB) +#define sed1375Screen1StartAddressRegisterLSB 0x0C +#define sed1375Screen1StartAddressRegisterMSB 0x0D + +// REG[0x0F] Screen 2 Start Address Register (LSB) +// REG[0x10] Screen 2 Start Address Register (MSB) +#define sed1375Screen2StartAddressRegisterLSB 0x0F +#define sed1375Screen2StartAddressRegisterMSB 0x10 + +// REG[0x12] Memory Address Offset Register +#define sed1375MemoryAddressOffsetRegister 0x12 + +// REG[0x13] Screen 1 Vertical Size Register (LSB) +// REG[0x14] Screen 1 Vertical Size Register (MSB) +#define sed1375Screen1VerticalSizeRegisterLSB 0x13 +#define sed1375Screen1VerticalSizeRegisterMSB 0x14 + +// REG[0x15] Look-Up Table Address Register +#define sed1375LookUpTableAddressRegister 0x15 +#define sed1375LookUpAutoIncrement 0x00 +#define sed1375LookUpRedTableSelect 0x10 +#define sed1375LookUpGrayGreenTableSelect 0x20 +#define sed1375LookUpBlueTableSelect 0x30 +#define sed1375LookUpTableAddressMask 0x0F + +// REG[0x16] Look-Up Table Bank Select Register +#define sed1375LookUpTableBankSelectRegister 0x16 +#define sed1375LookUpTableRedBank(n) (((n) & 0x03) << 4) +#define sed1375LookUpTableGreenBank(n) (((n) & 0x03) << 2) +#define sed1375LookUpTableBlueBank(n) ((n) & 0x03) +#define sed1375LookUpTableBank(n) (sed1375LookUpTableRedBank(n) | sed1375LookUpTableGreenBank(n) | sed1375LookUpTableBlueBank(n)) + +// REG[0x17] Look-Up Table Data Register +#define sed1375LookUpTableDataRegister 0x17 +#define sed1375LookUpTableDataMask 0x0F + +// REG[0x18] GPIO Configuration Control Register +#define sed1375GPIOConfigurationControlRegister 0x18 +#define sed1375GPIOPinOut(n, v) (((v) ? 1:0) << (n)) + +// REG[0x19] GPIO Status/Control Register +#define sed1375GPIOStatusControlRegister 0x19 +#define sed1375GPIOPinStatusMask(n) (1 << (n)) +#define sed1375GPIOPinSet(n, v) (((v) ? 1:0) << (n)) + +// REG[0x1A] Scratch Pad Register +#define sed1375ScratchPadRegister 0x1A + +// REG[0x1B] Portrait Mode Register +#define sed1375PortraitModeRegister 0x1B +#define sed1375LandscapeMode 0x00 +#define sed1375PortraitModeEnable 0x80 // bit 7 +#define sed1375X2SchemeSelect 0x40 // bit 6 +#define sed1375MCLKAutoDisable 0x04 // bit 2 +#define sed1375PCLKSelectBit1 0x02 // bit 1 +#define sed1375PCLKSelectBit0 0x01 // bit 0 + +// REG[0x1C] Line UInt8 Count Register (for Portrait Mode) +#define sed1375LineByteCountRegister 0x1C + +// REG[0x1D] ???? Register +#define sed1375UnusualRegister 0x1D +#define sed1375RepeatFrame 0x80 +#define sed1375Skip128FramesDuringPS 0x40 +#define sed1375OverlayEnable 0x20 +#define sed1375OverlayOperationBit1 0x10 +#define sed1375OverlayOperationBit0 0x08 +#define sed1375ForceHighClock 0x04 +#define sed1375FrameSkip 0x02 +#define sed1375FrameSkipStatus 0x01 + +// REG[0x1F] Test Mode Register +#define sed1375TestModeRegister 0x1F +#define sed1375TestMode(n) ((n & 0x03) << 6) +#define sed1375TestInput(n) ((n & 0x07) << 3) +#define sed1375TestOutputMask 0x07 +#define sed1375TestModeNormal 0x00 +#define sed1375TestModeUnusual sed1375TestMode(1) |