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| author |  Gael Guennebaud <g.gael@free.fr> | 2009-08-06 12:20:02 +0200 |
|---|---|---|
| committer | Gael Guennebaud <g.gael@free.fr> | 2009-08-06 12:20:02 +0200 |
| commit | 56d00779db6975fea0821a71abf6323f98a1f4c0 (patch) | |
| tree | 2e49e38c08bc6be41702a21b0987cd0b0c49e8fe /Eigen/src/Core/util | |
| parent | 6b2ab13ac54aff7ff15046d05b3f060a3f1f2044 (diff) | |
more product refactoring
Diffstat (limited to 'Eigen/src/Core/util')
| -rw-r--r-- | Eigen/src/Core/util/BlasUtil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Eigen/src/Core/util/BlasUtil.h b/Eigen/src/Core/util/BlasUtil.h index 216f2dd69..f4690c0ca 100644 --- a/Eigen/src/Core/util/BlasUtil.h +++ b/Eigen/src/Core/util/BlasUtil.h @@ -139,7 +139,7 @@ struct ei_product_blocking_traits // register block size along the N direction (must be either 2 or 4) nr = HalfRegisterCount/2, - // register block size along the M direction (this cannot be modified) + // register block size along the M direction (currently, this one cannot be modified) mr = 2 * PacketSize, // max cache block size along the K direction |