diff options
| author |  Gael Guennebaud <g.gael@free.fr> | 2013-10-28 17:48:32 +0100 |
|---|---|---|
| committer | Gael Guennebaud <g.gael@free.fr> | 2013-10-28 17:48:32 +0100 |
| commit | 11fbbc51faa17babefa439423bfa6b69c14fc9e8 (patch) | |
| tree | 13f21e300f0b7fc9b54d2dcc4d0b99bc85c4d370 /Eigen/src/Core/products | |
| parent | d3e84b747add85220119e951fff837ad9b25b8c8 (diff) | |
Fix bug #359: fix AlignedBit flag of CoeffBasedProduct thus enabling the vectorization of more matrix products
Diffstat (limited to 'Eigen/src/Core/products')
| -rw-r--r-- | Eigen/src/Core/products/CoeffBasedProduct.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Eigen/src/Core/products/CoeffBasedProduct.h b/Eigen/src/Core/products/CoeffBasedProduct.h index c06a0df1c..357e04cb0 100644 --- a/Eigen/src/Core/products/CoeffBasedProduct.h +++ b/Eigen/src/Core/products/CoeffBasedProduct.h @@ -85,7 +85,8 @@ struct traits<CoeffBasedProduct<LhsNested,RhsNested,NestingFlags> > Flags = ((unsigned int)(LhsFlags | RhsFlags) & HereditaryBits & ~RowMajorBit) | (EvalToRowMajor ? RowMajorBit : 0) | NestingFlags - | (LhsFlags & RhsFlags & AlignedBit) + | (CanVectorizeLhs ? (LhsFlags & AlignedBit) : 0) + | (CanVectorizeRhs ? (RhsFlags & AlignedBit) : 0) // TODO enable vectorization for mixed types | (SameType && (CanVectorizeLhs || CanVectorizeRhs) ? PacketAccessBit : 0), @@ -305,7 +306,6 @@ struct product_coeff_impl<InnerVectorizedTraversal, UnrollingIndex, Lhs, Rhs, Re { Packet pres; product_coeff_vectorized_unroller<UnrollingIndex+1-PacketSize, Lhs, Rhs, Packet>::run(row, col, lhs, rhs, pres); - product_coeff_impl<DefaultTraversal,UnrollingIndex,Lhs,Rhs,RetScalar>::run(row, col, lhs, rhs, res); res = predux(pres); } }; |