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+Changes in reSID version 0.13
+-----------------------------
+
+The internal DC levels of the MOS6581 have been double checked and
+corrected. The reason for the asymmetric scaling of the voice output
+has been found; there is a DC offset from the waveform D/A converter
+in addition to the DC offset from the envelope multiplying D/A
+converter. No selected waveform (N=P=S=T=0) yields minimum wave output
+level again.
+
+A bug in the fast version of the envelope clocking has been corrected.
+This bug could incorrectly invoke the ADSR delay emulation.
+
+
+Changes in reSID version 0.12
+-----------------------------
+
+A bug causing incorrect sample spacing in the new SAMPLE_FAST sample
+calculation has been corrected.
+
+Audio clipping has been added to guard against sample overflows.
+
+To support multi-channel sampling, sample interleaving has been added
+to the clock() interface.
+
+To support synchronization with an external timer, an interface for
+sample rate adjustment has been added.
+
+The internal DC levels have been corrected. No selected waveform
+(N=P=S=T=0) yields maximum wave output level. Furthermore, each voice
+in the MOS6581 independently contributes to the DC level in the mixer,
+and the mixer itself has a small DC offset as well. The MOS8580 has no
+DC offsets.
+
+The spline interpolation routine has been generalized to accept
+repeated points to introduce points of non-differentiability and
+discontinuity.
+
+A separate mapping from the FC registers to filter cutoff frequency
+has been included for the MOS8580, and the mapping for the MOS6581 has
+been refined.
+
+
+Changes in reSID version 0.11
+-----------------------------
+
+A new clock() interface has been added. This function generates audio
+samples into a buffer, greatly simplifying the task of writing driver
+code for reSID. It also facilitates more advanced audio sample
+generation, as described below.
+
+Three clocking methods are available: clocking at output sample
+frequency, clocking at cycle frequency with linear sample
+interpolation, and clocking at cycle frequency with audio resampling.
+
+Clocking at output sample frequency is fast, and yields acceptable
+sound quality, except for the SID combined waveforms, which have a
+very high frequency content.
+
+Clocking at cycle frequency with linear sample interpolation is
+approximately five to ten times slower at 44.1kHz sampling frequency,
+but the sound quality is improved because of the linear sample
+interpolation, and because some sampling noise is removed by the SID
+external filter, which attenuates signals above 16kHz.
+
+Finally, clocking at cycle frequency with audio resampling has a work
+rate which is independent of the sampling frequency; it is rather
+inversely proportional to the percentage of the bandwidth allocated
+to the filter transition band. This implies that e.g. with the
+transition band starting at ~ 20kHz, it is faster to generate 48kHz
+than 44.1kHz samples.
+
+Audio resampling is the theoretically correct method for sample
+generation, and delivers SID sound quality previously unheard of. This
+should make connoisseurs nod in appreciation, and for some time to
+come it could possibly also make people tear their hair over having to
+buy state of the art hardware to handle the obscene workload in real
+time. By trading off passband bandwidth for speed, real time
+processing is possible on current hardware. A 60% passband bandwidth
+is within the reach of reasonably fast machines, while maximum sound
+quality at 90% passband bandwidth, requiring four times the processing
+power, is not. Yet.
+
+
+Changes in reSID version 0.10
+-----------------------------
+
+Libtool is now used to build the library.
+
+To keep the filters stable it is necessary to clock them at above
+sample rate. The chip clocking code has been modified to only
+"overclock" the filters, not the whole chip. This yields a
+considerable speedup without noticeably lowering sound quality. Note
+that this is aimed at slow hardware, if possible the 1 cycle clock
+interface should be used to eliminate sampling noise.
+
+
+Changes in reSID version 0.9
+----------------------------
+
+The sum of the filter outputs is no longer weighted.
+
+
+Changes in reSID version 0.8
+----------------------------
+
+voice3off has no effect if voice 3 is routed through the filter.
+
+
+Changes in reSID version 0.7
+----------------------------
+
+The audio output filter in the C64, external to the SID chip, has been
+modeled.
+
+The mapping function between the FC register and filter cutoff frequency can
+now be specified with spline interpolation points. This facilitates
+interactive modification of the mapping function by graphical presentation of
+the interpolation curve. The implementation of this novel spline design is
+fast and general purpose, and should be well suited for use in other projects
+as well.
+
+Filtered output has been inverted compared to unfiltered output.
+
+Aging of the bus value obtained when reading write only registers has been
+partly implemented.
+
+To facilitate offline storage the complete state of SID can be read and
+written.
+
+
+Changes in reSID version 0.6
+----------------------------
+
+A special case in synchronization has been implemented.
+
+The Autoconf script is cleaned up to allow compilation in a separate directory.
+
+
+Changes in reSID version 0.5
+----------------------------
+
+Emulation of MOS8580 combined waveforms.
+
+Version string resid_version_string provided for e.g. Autoconf tests.
+The string has C linkage.
+
+
+Changes in reSID version 0.4
+----------------------------
+
+The implementation of the ADSR delay bug has been refined and should now be
+cycle exact.
+
+The patch for VICE has been removed since VICE 0.15 will include reSID support.
+
+
+Changes in reSID version 0.3
+----------------------------
+
+The reSID library has changed name from libmos6581.a to libresid.a
+
+The pulse+sawtooth combined waveform has been corrected.
+
+Pulse+test bit samples are implemented.
+
+The envelope rate periods have finally been exactly determined.
+
+A new SID bug, the ADSR boundary bug, has been discovered and implemented.
+This bug makes it possible to step from envelope level 0x00 to 0xff or from
+0xff to 0x00 in one step.
+
+One-cycle optimized overloads of the clock() functions have been implemented
+to facilitate sampling at 1MHz.
+
+The code has been further optimized for speed.
+
+
+Changes in reSID version 0.2
+----------------------------
+
+The implementation of the Envelope Generator has been rewritten to handle
+the infamous ADSR delay bug. All known envelope related bugs have been
+corrected.
+
+The maximum filter resonance is lowered to keep the filter stable.
+
+The reSID API has been simplified. Reading write only registers is allowed.