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authorGravatar Alexey Yakovenko <wakeroid@gmail.com>2010-06-28 22:20:55 +0200
committerGravatar Alexey Yakovenko <wakeroid@gmail.com>2010-06-28 22:20:55 +0200
commita255ff9f91e27fa06152210953e2cb35e52f37a9 (patch)
tree8edcecc2f2826c1a95627ef825db0849690e089f
parente8eba665eaa2befeab7edc54646dc5cd02b6e472 (diff)
ao plugin: reentrant arm7 emu; fixed dsf library loader
Diffstat
-rwxr-xr-xplugins/ao/ao.h2
-rw-r--r--plugins/ao/eng_dsf/aica.c20
-rw-r--r--plugins/ao/eng_dsf/aica.h6
-rw-r--r--plugins/ao/eng_dsf/arm7.c192
-rw-r--r--plugins/ao/eng_dsf/arm7.h35
-rw-r--r--plugins/ao/eng_dsf/arm7i.c715
-rw-r--r--plugins/ao/eng_dsf/arm7i.h2
-rw-r--r--plugins/ao/eng_dsf/arm7memil.c26
-rw-r--r--plugins/ao/eng_dsf/dc_hw.c68
-rw-r--r--plugins/ao/eng_dsf/dc_hw.h12
-rw-r--r--plugins/ao/eng_dsf/eng_dsf.c49
-rw-r--r--plugins/ao/eng_protos.h12
-rw-r--r--plugins/ao/eng_psf/eng_psf.c2
-rw-r--r--plugins/ao/eng_psf/eng_psf2.c2
-rw-r--r--plugins/ao/eng_psf/eng_spu.c2
-rw-r--r--plugins/ao/eng_qsf/eng_qsf.c2
-rw-r--r--plugins/ao/eng_ssf/eng_ssf.c2
-rw-r--r--plugins/ao/main.c8
-rw-r--r--plugins/ao/plugin.c4
19 files changed, 601 insertions, 560 deletions
diff --git a/plugins/ao/ao.h b/plugins/ao/ao.h
index a9b0f01a..f3503df8 100755
--- a/plugins/ao/ao.h
+++ b/plugins/ao/ao.h
@@ -204,7 +204,7 @@ int ao_get_lib(char *filename, uint8 **buffer, uint64 *length);
int ao_identify (char *buffer);
-void *ao_start (uint32 type, uint8 *buffer, uint32 size);
+void *ao_start (uint32 type, const char *name, uint8 *buffer, uint32 size);
int ao_stop (uint32 type, void *handle);
diff --git a/plugins/ao/eng_dsf/aica.c b/plugins/ao/eng_dsf/aica.c
index ad0cde3c..dc7cdf0b 100644
--- a/plugins/ao/eng_dsf/aica.c
+++ b/plugins/ao/eng_dsf/aica.c
@@ -175,7 +175,7 @@ struct _AICA
unsigned char *AICARAM;
UINT32 AICARAM_LENGTH;
char Master;
- void (*IntARMCB)(int irq);
+ void (*IntARMCB)(struct sARM7 *cpu, int irq);
INT32 *buffertmpl, *buffertmpr;
@@ -201,6 +201,8 @@ struct _AICA
int ARTABLE[64], DRTABLE[64];
struct _AICADSP DSP;
+
+ struct sARM7 *cpu;
};
static struct _AICA *AllocedAICA;
@@ -245,7 +247,7 @@ static void CheckPendingIRQ(struct _AICA *AICA)
if(AICA->MidiW!=AICA->MidiR)
{
AICA->IRQL = AICA->IrqMidi;
- AICA->IntARMCB(1);
+ AICA->IntARMCB(AICA->cpu, 1);
return;
}
if(!pend)
@@ -254,21 +256,21 @@ static void CheckPendingIRQ(struct _AICA *AICA)
if(en&0x40)
{
AICA->IRQL = AICA->IrqTimA;
- AICA->IntARMCB(1);
+ AICA->IntARMCB(AICA->cpu, 1);
return;
}
if(pend&0x80)
if(en&0x80)
{
AICA->IRQL = AICA->IrqTimBC;
- AICA->IntARMCB(1);
+ AICA->IntARMCB(AICA->cpu, 1);
return;
}
if(pend&0x100)
if(en&0x100)
{
AICA->IRQL = AICA->IrqTimBC;
- AICA->IntARMCB(1);
+ AICA->IntARMCB(AICA->cpu, 1);
return;
}
}
@@ -482,6 +484,7 @@ static void AICA_StopSlot(struct _SLOT *slot,int keyoff)
static void AICA_Init(struct _AICA *AICA, const struct AICAinterface *intf)
{
+ printf ("AICA_Init(cpu=%p)\n", intf->cpu);
int i=0;
AICA->IrqTimA = AICA->IrqTimBC = AICA->IrqMidi = 0;
@@ -503,10 +506,11 @@ static void AICA_Init(struct _AICA *AICA, const struct AICAinterface *intf)
if (intf->region)
{
- AICA->AICARAM = &dc_ram[0];
+ AICA->AICARAM = &intf->cpu->dc_ram[0];
AICA->AICARAM_LENGTH = 2*1024*1024;
AICA->DSP.AICARAM = (UINT16 *)AICA->AICARAM;
AICA->DSP.AICARAM_LENGTH = (2*1024*1024)/2;
+ AICA->cpu = intf->cpu;
}
}
@@ -786,7 +790,7 @@ static void AICA_UpdateRegR(struct _AICA *AICA, int reg)
unsigned short v=AICA->udata.data[0x8/2];
v&=0xff00;
v|=AICA->MidiStack[AICA->MidiR];
- AICA->IntARMCB(0); // cancel the IRQ
+ AICA->IntARMCB(AICA->cpu, 0); // cancel the IRQ
if(AICA->MidiR!=AICA->MidiW)
{
++AICA->MidiR;
@@ -852,7 +856,7 @@ static void AICA_w16(struct _AICA *AICA,unsigned int addr,unsigned short val)
if (val)
{
- AICA->IntARMCB(0);
+ AICA->IntARMCB(AICA->cpu, 0);
}
}
}
diff --git a/plugins/ao/eng_dsf/aica.h b/plugins/ao/eng_dsf/aica.h
index f01468f3..a3b1c3c8 100644
--- a/plugins/ao/eng_dsf/aica.h
+++ b/plugins/ao/eng_dsf/aica.h
@@ -15,13 +15,15 @@ typedef int8 data8_t;
typedef int16 data16_t;
typedef int32 data32_t;
typedef int offs_t;
+struct sARM7;
struct AICAinterface
{
int num;
+ struct sARM7 *cpu;
void *region[MAX_AICA];
int mixing_level[MAX_AICA]; /* volume */
- void (*irq_callback[MAX_AICA])(int state); /* irq callback */
+ void (*irq_callback[MAX_AICA])(struct sARM7 *cpu, int state); /* irq callback */
};
int AICA_sh_start(struct AICAinterface *intf);
@@ -41,4 +43,6 @@ WRITE16_HANDLER( AICA_1_w );
WRITE16_HANDLER( AICA_MidiIn );
READ16_HANDLER( AICA_MidiOutR );
+void *aica_start(const void *config);
+
#endif
diff --git a/plugins/ao/eng_dsf/arm7.c b/plugins/ao/eng_dsf/arm7.c
index 980c306f..570bf56a 100644
--- a/plugins/ao/eng_dsf/arm7.c
+++ b/plugins/ao/eng_dsf/arm7.c
@@ -15,14 +15,14 @@
// definitions and macros
/** Macro for accessing banked registers. */
-#define RX_BANK(t,r) (ARM7.Rx_bank [t][r - 8])
+#define RX_BANK(t,r) (cpu->Rx_bank [t][r - 8])
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// private functions
/** CPU Reset. */
-static void Reset (void);
+static void Reset (struct sARM7 *cpu);
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
@@ -43,171 +43,177 @@ static const int s_tabTryb [32] = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
// public functions
+struct sARM7* ARM7_Alloc ()
+{
+ struct sARM7 *cpu = malloc (sizeof (struct sARM7));
+ memset (cpu, 0, sizeof (struct sARM7));
+ return cpu;
+}
//--------------------------------------------------------------------------
/** ARM7 emulator init. */
-void ARM7_Init ()
+void ARM7_Init (struct sARM7 *cpu)
{
// sane startup values
- ARM7.fiq = 0;
- ARM7.irq = 0;
- ARM7.carry = 0;
- ARM7.overflow = 0;
- ARM7.flagi = FALSE;
- ARM7.cykle = 0;
+ cpu->fiq = 0;
+ cpu->irq = 0;
+ cpu->carry = 0;
+ cpu->overflow = 0;
+ cpu->flagi = FALSE;
+ cpu->cykle = 0;
// reset will do the rest
- ARM7_HardReset ();
+ ARM7_HardReset (cpu);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Power-ON reset. */
-void ARM7_HardReset ()
+void ARM7_HardReset (struct sARM7 *cpu)
{
// CPSR that makes sense
- ARM7.Rx [ARM7_CPSR] = ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc;
- Reset ();
+ cpu->Rx [ARM7_CPSR] = ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc;
+ Reset (cpu);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Hardware reset via /RESET line. */
-void ARM7_SoftReset ()
+void ARM7_SoftReset (struct sARM7 *cpu)
{
- Reset ();
+ Reset (cpu);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** CPSR update, possibly changing operating mode. */
-void ARM7_SetCPSR (ARM7_REG sr)
+void ARM7_SetCPSR (struct sARM7 *cpu, ARM7_REG sr)
{
int stary, nowy;
- stary = s_tabTryb [ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR])];
+ stary = s_tabTryb [ARM7_CPSR_M (cpu->Rx [ARM7_CPSR])];
nowy = s_tabTryb [ARM7_CPSR_M (sr)];
// do we have to change modes?
if (nowy != stary)
{
// save this mode registers
- RX_BANK (stary, ARM7_SP) = ARM7.Rx [ARM7_SP],
- RX_BANK (stary, ARM7_LR) = ARM7.Rx [ARM7_LR],
- RX_BANK (stary, ARM7_SPSR) = ARM7.Rx [ARM7_SPSR];
+ RX_BANK (stary, ARM7_SP) = cpu->Rx [ARM7_SP],
+ RX_BANK (stary, ARM7_LR) = cpu->Rx [ARM7_LR],
+ RX_BANK (stary, ARM7_SPSR) = cpu->Rx [ARM7_SPSR];
if (stary == ARM7_MODE_fiq)
{
// copy R8-R12
- RX_BANK (ARM7_MODE_fiq, 8) = ARM7.Rx [8],
- RX_BANK (ARM7_MODE_fiq, 9) = ARM7.Rx [9],
- RX_BANK (ARM7_MODE_fiq, 10) = ARM7.Rx [10],
- RX_BANK (ARM7_MODE_fiq, 11) = ARM7.Rx [11],
- RX_BANK (ARM7_MODE_fiq, 12) = ARM7.Rx [12];
- ARM7.Rx [8] = RX_BANK (ARM7_MODE_usr, 8),
- ARM7.Rx [9] = RX_BANK (ARM7_MODE_usr, 9),
- ARM7.Rx [10] = RX_BANK (ARM7_MODE_usr, 10),
- ARM7.Rx [11] = RX_BANK (ARM7_MODE_usr, 11),
- ARM7.Rx [12] = RX_BANK (ARM7_MODE_usr, 12);
+ RX_BANK (ARM7_MODE_fiq, 8) = cpu->Rx [8],
+ RX_BANK (ARM7_MODE_fiq, 9) = cpu->Rx [9],
+ RX_BANK (ARM7_MODE_fiq, 10) = cpu->Rx [10],
+ RX_BANK (ARM7_MODE_fiq, 11) = cpu->Rx [11],
+ RX_BANK (ARM7_MODE_fiq, 12) = cpu->Rx [12];
+ cpu->Rx [8] = RX_BANK (ARM7_MODE_usr, 8),
+ cpu->Rx [9] = RX_BANK (ARM7_MODE_usr, 9),
+ cpu->Rx [10] = RX_BANK (ARM7_MODE_usr, 10),
+ cpu->Rx [11] = RX_BANK (ARM7_MODE_usr, 11),
+ cpu->Rx [12] = RX_BANK (ARM7_MODE_usr, 12);
}
// fetch new mode registers
- ARM7.Rx [ARM7_SP] = RX_BANK (nowy, ARM7_SP),
- ARM7.Rx [ARM7_LR] = RX_BANK (nowy, ARM7_LR),
- ARM7.Rx [ARM7_SPSR] = RX_BANK (nowy, ARM7_SPSR);
+ cpu->Rx [ARM7_SP] = RX_BANK (nowy, ARM7_SP),
+ cpu->Rx [ARM7_LR] = RX_BANK (nowy, ARM7_LR),
+ cpu->Rx [ARM7_SPSR] = RX_BANK (nowy, ARM7_SPSR);
if (nowy == ARM7_MODE_fiq)
{
// copy R8-R12
- RX_BANK (ARM7_MODE_usr, 8) = ARM7.Rx [8],
- RX_BANK (ARM7_MODE_usr, 9) = ARM7.Rx [9],
- RX_BANK (ARM7_MODE_usr, 10) = ARM7.Rx [10],
- RX_BANK (ARM7_MODE_usr, 11) = ARM7.Rx [11],
- RX_BANK (ARM7_MODE_usr, 12) = ARM7.Rx [12];
- ARM7.Rx [8] = RX_BANK (ARM7_MODE_fiq, 8),
- ARM7.Rx [9] = RX_BANK (ARM7_MODE_fiq, 9),
- ARM7.Rx [10] = RX_BANK (ARM7_MODE_fiq, 10),
- ARM7.Rx [11] = RX_BANK (ARM7_MODE_fiq, 11),
- ARM7.Rx [12] = RX_BANK (ARM7_MODE_fiq, 12);
+ RX_BANK (ARM7_MODE_usr, 8) = cpu->Rx [8],
+ RX_BANK (ARM7_MODE_usr, 9) = cpu->Rx [9],
+ RX_BANK (ARM7_MODE_usr, 10) = cpu->Rx [10],
+ RX_BANK (ARM7_MODE_usr, 11) = cpu->Rx [11],
+ RX_BANK (ARM7_MODE_usr, 12) = cpu->Rx [12];
+ cpu->Rx [8] = RX_BANK (ARM7_MODE_fiq, 8),
+ cpu->Rx [9] = RX_BANK (ARM7_MODE_fiq, 9),
+ cpu->Rx [10] = RX_BANK (ARM7_MODE_fiq, 10),
+ cpu->Rx [11] = RX_BANK (ARM7_MODE_fiq, 11),
+ cpu->Rx [12] = RX_BANK (ARM7_MODE_fiq, 12);
}
}
// new CPSR value
- ARM7.Rx [ARM7_CPSR] = sr;
+ cpu->Rx [ARM7_CPSR] = sr;
// mode change could've enabled interrups, so we test for those and set
// appropriate flag for the instruction loop to catch
- if (ARM7.fiq)
- ARM7.flagi |= ARM7_FL_FIQ;
+ if (cpu->fiq)
+ cpu->flagi |= ARM7_FL_FIQ;
#ifndef ARM7_DREAMCAST
- if (ARM7.irq)
- ARM7.flagi |= ARM7_FL_IRQ;
+ if (cpu->irq)
+ cpu->flagi |= ARM7_FL_IRQ;
#endif
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Sets FIQ line state. */
-void ARM7_SetFIQ (int stan)
+void ARM7_SetFIQ (struct sARM7 *cpu, int stan)
{
stan = stan ? TRUE : FALSE;
// we catch changes only
- if (stan ^ ARM7.fiq)
+ if (stan ^ cpu->fiq)
{
- ARM7.fiq = stan;
- if (ARM7.fiq)
- ARM7.flagi |= ARM7_FL_FIQ;
+ cpu->fiq = stan;
+ if (cpu->fiq)
+ cpu->flagi |= ARM7_FL_FIQ;
}
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Sets IRQ line state. */
-void ARM7_SetIRQ (int stan)
+void ARM7_SetIRQ (struct sARM7 *cpu, int stan)
{
stan = stan ? TRUE : FALSE;
// we catch changes only
- if (stan ^ ARM7.irq)
+ if (stan ^ cpu->irq)
{
- ARM7.irq = stan;
- if (ARM7.irq)
- ARM7.flagi |= ARM7_FL_IRQ;
+ cpu->irq = stan;
+ if (cpu->irq)
+ cpu->flagi |= ARM7_FL_IRQ;
}
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Tests for pending interrupts, switches to one if possible. */
-void ARM7_CheckIRQ ()
+void ARM7_CheckIRQ (struct sARM7 *cpu)
{
- UINT32 sr = ARM7.Rx [ARM7_CPSR];
+ UINT32 sr = cpu->Rx [ARM7_CPSR];
// clear all interrupt flags
- ARM7.flagi &= ~(ARM7_FL_FIQ | ARM7_FL_IRQ);
+ cpu->flagi &= ~(ARM7_FL_FIQ | ARM7_FL_IRQ);
// check for pending interrupts we can switch to
// (FIQ can interrupt IRQ, but not the other way around)
- if (ARM7.fiq)
+ if (cpu->fiq)
{
if (!(sr & ARM7_CPSR_F))
{
// FIQ
- ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_fiq) | ARM7_CPSR_F | ARM7_CPSR_I);
- ARM7.Rx [ARM7_SPSR] = sr;
+ ARM7_SetCPSR (cpu, ARM7_CPSR_MX (sr, ARM7_CPSR_M_fiq) | ARM7_CPSR_F | ARM7_CPSR_I);
+ cpu->Rx [ARM7_SPSR] = sr;
// set new PC (return from interrupt will subtract 4)
- ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC] + 4;
- ARM7.Rx [ARM7_PC] = 0x0000001c;
+ cpu->Rx [ARM7_LR] = cpu->Rx [ARM7_PC] + 4;
+ cpu->Rx [ARM7_PC] = 0x0000001c;
}
}
#ifndef ARM7_DREAMCAST
- if (ARM7.irq)
+ if (cpu->irq)
{
if (!(sr & ARM7_CPSR_I))
{
// IRQ
- ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_irq) | ARM7_CPSR_I);
- ARM7.Rx [ARM7_SPSR] = sr;
+ ARM7_SetCPSR (cpu, ARM7_CPSR_MX (sr, ARM7_CPSR_M_irq) | ARM7_CPSR_I);
+ cpu->Rx [ARM7_SPSR] = sr;
// set new PC (return from interrupt will subtract 4)
- ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC] + 4;
- ARM7.Rx [ARM7_PC] = 0x00000018;
- ARM7.irq = 0;
+ cpu->Rx [ARM7_LR] = cpu->Rx [ARM7_PC] + 4;
+ cpu->Rx [ARM7_PC] = 0x00000018;
+ cpu->irq = 0;
}
}
#endif
@@ -216,38 +222,38 @@ void ARM7_CheckIRQ ()
//--------------------------------------------------------------------------
/** Single step. */
-void ARM7_Step ()
+void ARM7_Step (struct sARM7 *cpu)
{
// make a step
#ifdef ARM7_THUMB
- if (ARM7.Rx[ARM7_CPSR] & ARM7_CPSR_T)
+ if (cpu->Rx[ARM7_CPSR] & ARM7_CPSR_T)
{
- ARM7i_Thumb_Step();
+ ARM7i_Thumb_Step(cpu);
}
else
#endif
{
- ARM7i_Step ();
+ ARM7i_Step (cpu);
}
// and test interrupts
- ARM7_CheckIRQ ();
+ ARM7_CheckIRQ (cpu);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Runs emulation for at least n cycles, returns actual amount of cycles
burned - normal interpreter. */
-int ARM7_Execute (int n)
+int ARM7_Execute (struct sARM7 *cpu, int n)
{
- ARM7.cykle = 0;
- while (ARM7.cykle < n)
+ cpu->cykle = 0;
+ while (cpu->cykle < n)
{
- ARM7_CheckIRQ ();
- while (!ARM7.flagi && ARM7.cykle < n)
+ ARM7_CheckIRQ (cpu);
+ while (!cpu->flagi && cpu->cykle < n)
// make one step, sum up cycles
- ARM7.cykle += ARM7i_Step ();
+ cpu->cykle += ARM7i_Step (cpu);
}
- return ARM7.cykle;
+ return cpu->cykle;
}
//--------------------------------------------------------------------------
@@ -257,18 +263,18 @@ int ARM7_Execute (int n)
//--------------------------------------------------------------------------
/** CPU Reset. */
-void Reset (void)
+void Reset (struct sARM7 *cpu)
{
// clear ALU flags
- ARM7.carry = 0;
- ARM7.overflow = 0;
+ cpu->carry = 0;
+ cpu->overflow = 0;
// test CPSR mode and pick a valid one if necessary
- if (s_tabTryb [ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR])] < 0)
- ARM7.Rx [ARM7_CPSR] = ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc;
+ if (s_tabTryb [ARM7_CPSR_M (cpu->Rx [ARM7_CPSR])] < 0)
+ cpu->Rx [ARM7_CPSR] = ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc;
// set up registers according to manual
- RX_BANK (ARM7_MODE_svc, ARM7_LR) = ARM7.Rx [ARM7_PC];
- RX_BANK (ARM7_MODE_svc, ARM7_SPSR) = ARM7.Rx [ARM7_CPSR];
- ARM7_SetCPSR (ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc);
- ARM7.Rx [ARM7_PC] = 0x00000000;
+ RX_BANK (ARM7_MODE_svc, ARM7_LR) = cpu->Rx [ARM7_PC];
+ RX_BANK (ARM7_MODE_svc, ARM7_SPSR) = cpu->Rx [ARM7_CPSR];
+ ARM7_SetCPSR (cpu, ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc);
+ cpu->Rx [ARM7_PC] = 0x00000000;
}
//--------------------------------------------------------------------------
diff --git a/plugins/ao/eng_dsf/arm7.h b/plugins/ao/eng_dsf/arm7.h
index 41cb9b56..dea6aa26 100644
--- a/plugins/ao/eng_dsf/arm7.h
+++ b/plugins/ao/eng_dsf/arm7.h
@@ -8,6 +8,7 @@
#define _ARM7_h_
#include "cpuintrf.h"
+#include "aica.h"
//--------------------------------------------------------------------------
// definitions and macros
@@ -115,41 +116,43 @@ struct sARM7
UINT32 kod;
/** Cycle counter. */
int cykle;
- };
- //--------------------------------------------------------------------------
- //--------------------------------------------------------------------------
- /** ARM7 state. */
-extern struct sARM7 ARM7;
+ uint8 dc_ram[8*1024*1024];
+
+ struct AICAinterface aica_interface;
+ };
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// public procedures
+ /** ARM7 allocate spu state. */
+struct sARM7* ARM7_Alloc (void);
+
/** ARM7 emulator init. */
-void ARM7_Init (void);
+void ARM7_Init (struct sARM7 *cpu);
/** Power-ON reset. */
-void ARM7_HardReset (void);
+void ARM7_HardReset (struct sARM7 *cpu);
/** Hardware reset via /RESET line. */
-void ARM7_SoftReset (void);
+void ARM7_SoftReset (struct sARM7 *cpu);
/** CPSR update, possibly changing operating mode. */
-void ARM7_SetCPSR (ARM7_REG sr);
+void ARM7_SetCPSR (struct sARM7 *cpu, ARM7_REG sr);
/** Sets FIQ line state. */
-void ARM7_SetFIQ (int stan);
+void ARM7_SetFIQ (struct sARM7 *cpu, int stan);
/** Sets IRQ line state. */
-void ARM7_SetIRQ (int stan);
+void ARM7_SetIRQ (struct sARM7 *cpu, int stan);
/** Tests for pending interrupts, switches to one if possible. */
-void ARM7_CheckIRQ (void);
+void ARM7_CheckIRQ (struct sARM7 *cpu);
/** Single step. */
-void ARM7_Step (void);
+void ARM7_Step (struct sARM7 *cpu);
/** Runs emulation for at least n cycles, returns actual amount of cycles
burned - normal interpreter. */
-int ARM7_Execute (int n);
+int ARM7_Execute (struct sARM7 *cpu, int n);
//--------------------------------------------------------------------------
enum
@@ -159,7 +162,7 @@ enum
};
#ifdef ENABLE_DEBUGGER
-extern UINT32 arm7_disasm( char *pBuf, UINT32 pc, UINT32 opcode );
-extern UINT32 thumb_disasm( char *pBuf, UINT32 pc, UINT16 opcode );
+extern UINT32 arm7_disasm( struct sARM7 *cpu, char *pBuf, UINT32 pc, UINT32 opcode );
+extern UINT32 thumb_disasm( struct sARM7 *cpu, char *pBuf, UINT32 pc, UINT16 opcode );
#endif
#endif
diff --git a/plugins/ao/eng_dsf/arm7i.c b/plugins/ao/eng_dsf/arm7i.c
index cb6c7106..1b831857 100644
--- a/plugins/ao/eng_dsf/arm7i.c
+++ b/plugins/ao/eng_dsf/arm7i.c
@@ -6,6 +6,7 @@
#include "arm7.h"
#include "arm7i.h"
+#include "dc_hw.h"
//--------------------------------------------------------------------------
// definitions and macros
@@ -49,85 +50,85 @@
// private functions
/** Condition EQ. */
-static int R_WEQ (void);
+static int R_WEQ (struct sARM7 *cpu);
/** Condition NE. */
-static int R_WNE (void);
+static int R_WNE (struct sARM7 *cpu);
/** Condition CS. */
-static int R_WCS (void);
+static int R_WCS (struct sARM7 *cpu);
/** Condition CC. */
-static int R_WCC (void);
+static int R_WCC (struct sARM7 *cpu);
/** Condition MI. */
-static int R_WMI (void);
+static int R_WMI (struct sARM7 *cpu);
/** Condition PL. */
-static int R_WPL (void);
+static int R_WPL (struct sARM7 *cpu);
/** Condition VS. */
-static int R_WVS (void);
+static int R_WVS (struct sARM7 *cpu);
/** Condition VC. */
-static int R_WVC (void);
+static int R_WVC (struct sARM7 *cpu);
/** Condition HI. */
-static int R_WHI (void);
+static int R_WHI (struct sARM7 *cpu);
/** Condition LS. */
-static int R_WLS (void);
+static int R_WLS (struct sARM7 *cpu);
/** Condition GE. */
-static int R_WGE (void);
+static int R_WGE (struct sARM7 *cpu);
/** Condition LT. */
-static int R_WLT (void);
+static int R_WLT (struct sARM7 *cpu);
/** Condition GT. */
-static int R_WGT (void);
+static int R_WGT (struct sARM7 *cpu);
/** Condition LE. */
-static int R_WLE (void);
+static int R_WLE (struct sARM7 *cpu);
/** Condition AL. */
-static int R_WAL (void);
+static int R_WAL (struct sARM7 *cpu);
/** Undefined condition. */
-static int R_Wxx (void);
+static int R_Wxx (struct sARM7 *cpu);
/** Calculates barrel shifter output. */
-static UINT32 WyliczPrzes (void);
+static UINT32 WyliczPrzes (struct sARM7 *cpu);
/** Logical shift left. */
-static UINT32 LSL_x (UINT32 w, int i);
+static UINT32 LSL_x (struct sARM7 *cpu, UINT32 w, int i);
/** Logical shift right. */
-static UINT32 LSR_x (UINT32 w, int i);
+static UINT32 LSR_x (struct sARM7 *cpu, UINT32 w, int i);
/** Arithmetic shift right. */
-static UINT32 ASR_x (UINT32 w, int i);
+static UINT32 ASR_x (struct sARM7 *cpu, UINT32 w, int i);
/** Rotate right. */
-static UINT32 ROR_x (UINT32 w, int i);
+static UINT32 ROR_x (struct sARM7 *cpu, UINT32 w, int i);
/** Rotate right extended. */
-static UINT32 RRX_1 (UINT32 w);
+static UINT32 RRX_1 (struct sARM7 *cpu, UINT32 w);
/** Group 00x opcodes. */
-static void R_G00x (void);
+static void R_G00x (struct sARM7 *cpu);
/** Multiply instructions. */
-static void R_MUL_MLA (void);
+static void R_MUL_MLA (struct sARM7 *cpu);
/** Single data swap. */
-static void R_SWP (void);
+static void R_SWP (struct sARM7 *cpu);
/** PSR Transfer. */
-static void R_PSR (void);
+static void R_PSR (struct sARM7 *cpu);
/** Data processing instructions. */
-static void R_DP (void);
+static void R_DP (struct sARM7 *cpu);
/** Data processing result writeback. */
-static void R_WynikDP (ARM7_REG w);
+static void R_WynikDP (struct sARM7 *cpu, ARM7_REG w);
/** Data processing flags writeback. */
-static void R_FlagiDP (ARM7_REG w);
+static void R_FlagiDP (struct sARM7 *cpu, ARM7_REG w);
/** Single data transfer. */
-static void R_SDT (void);
+static void R_SDT (struct sARM7 *cpu);
/** Rozkaz "Undefined". */
-static void R_Und ();
+static void R_Und (struct sARM7 *cpu);
/** Block Data Transfer. */
-static void R_BDT ();
+static void R_BDT (struct sARM7 *cpu);
/** Block load instructions. */
-static void R_LDM (int Rn, UINT32 adres);
+static void R_LDM (struct sARM7 *cpu, int Rn, UINT32 adres);
/** Block store instructions. */
-static void R_STM (int Rn, UINT32 adres);
+static void R_STM (struct sARM7 *cpu, int Rn, UINT32 adres);
/** Branch/Branch with link. */
-static void R_B_BL (void);
+static void R_B_BL (struct sARM7 *cpu);
/** Group 110 opcodes. */
-static void R_G110 (void);
+static void R_G110 (struct sARM7 *cpu);
/** Group 111 opcodes. */
-static void R_G111 (void);
+static void R_G111 (struct sARM7 *cpu);
#ifdef ARM7_THUMB
/** Halfword and Signed Data Transfer. */
-static void R_HSDT ();
+static void R_HSDT (struct sARM7 *cpu);
#endif
//--------------------------------------------------------------------------
@@ -135,10 +136,10 @@ static void R_HSDT ();
// private data
/** Flag testing functions for conditional execution. */
-static int (*s_tabWar [16]) (void) = {R_WEQ, R_WNE, R_WCS, R_WCC, R_WMI, R_WPL,
+static int (*s_tabWar [16]) (struct sARM7 *cpu) = {R_WEQ, R_WNE, R_WCS, R_WCC, R_WMI, R_WPL,
R_WVS, R_WVC, R_WHI, R_WLS, R_WGE, R_WLT, R_WGT, R_WLE, R_WAL, R_Wxx};
/** Handler table for instruction groups. */
-static void (*s_tabGrup [8]) (void) = {R_G00x, R_G00x, R_SDT, R_SDT, R_BDT,
+static void (*s_tabGrup [8]) (struct sARM7 *cpu) = {R_G00x, R_G00x, R_SDT, R_SDT, R_BDT,
R_B_BL, R_G110, R_G111};
/** Data processing instructions split to arithmetic and logical. */
static int s_tabAL [16] = {FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
@@ -154,17 +155,17 @@ static int s_cykle;
//--------------------------------------------------------------------------
/** Single step, returns number of burned cycles. */
-int ARM7i_Step ()
+int ARM7i_Step (struct sARM7 *cpu)
{
- ARM7.kod = arm7_read_32 (ARM7.Rx [ARM7_PC] & ~3);
+ cpu->kod = arm7_read_32 (cpu, cpu->Rx [ARM7_PC] & ~3);
// we increment PC here, and if there's a load from memory it will simply
// overwrite it (all PC modyfing code should be aware of this)
- ARM7.Rx [ARM7_PC] += 4;
+ cpu->Rx [ARM7_PC] += 4;
s_cykle = 2;
// condition test and group selection
- if (s_tabWar [(ARM7.kod >> 28) & 15] ())
- s_tabGrup [(ARM7.kod >> 25) & 7] ();
+ if (s_tabWar [(cpu->kod >> 28) & 15] (cpu))
+ s_tabGrup [(cpu->kod >> 25) & 7] (cpu);
return s_cykle;
}
//--------------------------------------------------------------------------
@@ -175,139 +176,139 @@ int ARM7i_Step ()
//--------------------------------------------------------------------------
/** Condition EQ. */
-int R_WEQ ()
+int R_WEQ (struct sARM7 *cpu)
{
// "Z set"
- return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z;
+ return cpu->Rx [ARM7_CPSR] & ARM7_CPSR_Z;
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition NE. */
-int R_WNE ()
+int R_WNE (struct sARM7 *cpu)
{
// "Z clear"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z);
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_Z);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition CS. */
-int R_WCS ()
+int R_WCS (struct sARM7 *cpu)
{
// "C set"
- return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C;
+ return cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C;
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition CC. */
-int R_WCC ()
+int R_WCC (struct sARM7 *cpu)
{
// "C clear"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C);
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition MI. */
-int R_WMI ()
+int R_WMI (struct sARM7 *cpu)
{
// "N set"
- return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N;
+ return cpu->Rx [ARM7_CPSR] & ARM7_CPSR_N;
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition PL. */
-int R_WPL ()
+int R_WPL (struct sARM7 *cpu)
{
// "N clear"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N);
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_N);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition VS. */
-int R_WVS ()
+int R_WVS (struct sARM7 *cpu)
{
// "V set"
- return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V;
+ return cpu->Rx [ARM7_CPSR] & ARM7_CPSR_V;
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition VC. */
-int R_WVC ()
+int R_WVC (struct sARM7 *cpu)
{
// "V clear"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V);
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_V);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition HI. */
-int R_WHI ()
+int R_WHI (struct sARM7 *cpu)
{
// "C set and Z clear"
- return (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) &&\
- !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z);
+ return (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) &&\
+ !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_Z);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition LS. */
-int R_WLS ()
+int R_WLS (struct sARM7 *cpu)
{
// "C clear or Z set"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ||\
- (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z);
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ||\
+ (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_Z);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition GE. */
-int R_WGE ()
+int R_WGE (struct sARM7 *cpu)
{
// "N equals V"
- return (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
- (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V) || !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
- !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V);
+ return (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
+ (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_V) || !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
+ !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_V);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition LT. */
-int R_WLT ()
+int R_WLT (struct sARM7 *cpu)
{
// "N not equal to V"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
- (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V) || (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
- !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V);
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
+ (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_V) || (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\
+ !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_V);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition GT. */
-int R_WGT ()
+int R_WGT (struct sARM7 *cpu)
{
// "Z clear AND (N equals V)"
- return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z) && R_WGE ();
+ return !(cpu->Rx [ARM7_CPSR] & ARM7_CPSR_Z) && R_WGE (cpu);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition LE. */
-int R_WLE ()
+int R_WLE (struct sARM7 *cpu)
{
// "Z set OR (N not equal to V)"
- return (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z) || R_WLT ();
+ return (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_Z) || R_WLT (cpu);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Condition AL. */
-int R_WAL ()
+int R_WAL (struct sARM7 *cpu)
{
// "(ignored)"
return TRUE;
@@ -316,7 +317,7 @@ int R_WAL ()
//--------------------------------------------------------------------------
/** Undefined condition. */
-int R_Wxx ()
+int R_Wxx (struct sARM7 *cpu)
{
// behaviour undefined
return FALSE;
@@ -325,45 +326,45 @@ int R_Wxx ()
//--------------------------------------------------------------------------
/** Calculates barrel shifter output. */
-UINT32 WyliczPrzes ()
+UINT32 WyliczPrzes (struct sARM7 *cpu)
{
int Rm, Rs, i;
UINT32 w;
// Rm is source for the shift operation
- Rm = ARM7.kod & 15;
+ Rm = cpu->kod & 15;
- if (ARM7.kod & (1 << 4))
+ if (cpu->kod & (1 << 4))
{
s_cykle++;
// shift count in Rs (8 lowest bits)
if (Rm != ARM7_PC)
- w = ARM7.Rx [Rm];
+ w = cpu->Rx [Rm];
else
- w = (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT;
+ w = (cpu->Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT;
// Rs can't be PC
- Rs = (ARM7.kod >> 8) & 15;
- i = (UINT8)ARM7.Rx [Rs];
+ Rs = (cpu->kod >> 8) & 15;
+ i = (UINT8)cpu->Rx [Rs];
if (i == 0)
{
// special case
- ARM7.carry = (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0;
+ cpu->carry = (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0;
return w;
}
- switch ((ARM7.kod >> 5) & 3)
+ switch ((cpu->kod >> 5) & 3)
{
case 0:
- w = LSL_x (w, i);
+ w = LSL_x (cpu, w, i);
break;
case 1:
- w = LSR_x (w, i);
+ w = LSR_x (cpu, w, i);
break;
case 2:
- w = ASR_x (w, i);
+ w = ASR_x (cpu, w, i);
break;
case 3:
- w = ROR_x (w, i);
+ w = ROR_x (cpu, w, i);
break;
}
}
@@ -371,33 +372,33 @@ UINT32 WyliczPrzes ()
{
// shift count as immediate in opcode
if (Rm != ARM7_PC)
- w = ARM7.Rx [Rm];
+ w = cpu->Rx [Rm];
else
- w = (ARM7.Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT;
- i = (ARM7.kod >> 7) & 31;
+ w = (cpu->Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT;
+ i = (cpu->kod >> 7) & 31;
- switch ((ARM7.kod >> 5) & 3)
+ switch ((cpu->kod >> 5) & 3)
{
case 0:
- w = LSL_x (w, i);
+ w = LSL_x (cpu, w, i);
break;
case 1:
if (i > 0)
- w = LSR_x (w, i);
+ w = LSR_x (cpu, w, i);
else
- w = LSR_x (w, 32);
+ w = LSR_x (cpu, w, 32);
break;
case 2:
if (i > 0)
- w = ASR_x (w, i);
+ w = ASR_x (cpu, w, i);
else
- w = ASR_x (w, 32);
+ w = ASR_x (cpu, w, 32);
break;
case 3:
if (i > 0)
- w = ROR_x (w, i);
+ w = ROR_x (cpu, w, i);
else
- w = RRX_1 (w);
+ w = RRX_1 (cpu, w);
break;
}
}
@@ -407,28 +408,28 @@ UINT32 WyliczPrzes ()
//--------------------------------------------------------------------------
/** Logical shift left. */
-UINT32 LSL_x (UINT32 w, int i)
+UINT32 LSL_x (struct sARM7 *cpu, UINT32 w, int i)
{
// LSL #0 copies C into carry out and returns unmodified value
if (i == 0)
{
- ARM7.carry = (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0;
+ cpu->carry = (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0;
return w;
}
// LSL #32 copies LSB to carry out and returns zero
if (i == 32)
{
- ARM7.carry = w & 1;
+ cpu->carry = w & 1;
return 0;
}
// LSL > #32 returns zero for both carry and output
if (i > 32)
{
- ARM7.carry = 0;
+ cpu->carry = 0;
return 0;
}
// normal shift
- ARM7.carry = (w & (1 << (32 - i))) ? 1 : 0;
+ cpu->carry = (w & (1 << (32 - i))) ? 1 : 0;
w = SHL (w, i);
return w;
}
@@ -436,22 +437,22 @@ UINT32 LSL_x (UINT32 w, int i)
//--------------------------------------------------------------------------
/** Logical shift right. */
-UINT32 LSR_x (UINT32 w, int i)
+UINT32 LSR_x (struct sARM7 *cpu, UINT32 w, int i)
{
// LSR #32 copies MSB to carry out and returns zero
if (i == 32)
{
- ARM7.carry = (w & (1 << 31)) ? 1 : 0;
+ cpu->carry = (w & (1 << 31)) ? 1 : 0;
return 0;
}
// LSR > #32 returns zero for both carry and output
if (i > 32)
{
- ARM7.carry = 0;
+ cpu->carry = 0;
return 0;
}
// normal shift
- ARM7.carry = (w & (1 << (i - 1))) ? 1 : 0;
+ cpu->carry = (w & (1 << (i - 1))) ? 1 : 0;
w = SHR (w, i);
return w;
}
@@ -459,22 +460,22 @@ UINT32 LSR_x (UINT32 w, int i)
//--------------------------------------------------------------------------
/** Arithmetic shift right. */
-UINT32 ASR_x (UINT32 w, int i)
+UINT32 ASR_x (struct sARM7 *cpu, UINT32 w, int i)
{
// ASR >= #32 carry out and output value depends on the minus sign
if (i >= 32)
{
if (w & (1 << 31))
{
- ARM7.carry = 1;
+ cpu->carry = 1;
return ~0;
}
- ARM7.carry = 0;
+ cpu->carry = 0;
return 0;
}
// normal shift
- ARM7.carry = (w & (1 << (i - 1))) ? 1 : 0;
+ cpu->carry = (w & (1 << (i - 1))) ? 1 : 0;
w = SAR (w, i);
return w;
}
@@ -482,18 +483,18 @@ UINT32 ASR_x (UINT32 w, int i)
//--------------------------------------------------------------------------
/** Rotate right. */
-UINT32 ROR_x (UINT32 w, int i)
+UINT32 ROR_x (struct sARM7 *cpu, UINT32 w, int i)
{
// mask count to [0; 31]
i &= 0x1f;
// ROR #32,#64,etc. copies MSB into carry out and returns unmodified value
if (i == 0)
{
- ARM7.carry = (w & (1 << 31)) ? 1 : 0;
+ cpu->carry = (w & (1 << 31)) ? 1 : 0;
return w;
}
// normal shift
- ARM7.carry = (w & (1 << (i-1))) ? 1 : 0;
+ cpu->carry = (w & (1 << (i-1))) ? 1 : 0;
w = ROR (w, i);
return w;
}
@@ -501,74 +502,74 @@ UINT32 ROR_x (UINT32 w, int i)
//--------------------------------------------------------------------------
/** Rotate right extended. */
-UINT32 RRX_1 (UINT32 w)
+UINT32 RRX_1 (struct sARM7 *cpu, UINT32 w)
{
// same as RCR by 1 in IA32
- ARM7.carry = w & 1;
- return (w >> 1) | ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) << 2);
+ cpu->carry = w & 1;
+ return (w >> 1) | ((cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) << 2);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Group 00x opcodes. */
-void R_G00x ()
+void R_G00x (struct sARM7 *cpu)
{
#ifdef ARM7_THUMB
// 24 constant bits
- if ((ARM7.kod & 0x0ffffff0) == 0x012fff10) // BX - branch with possible mode transfer
+ if ((cpu->kod & 0x0ffffff0) == 0x012fff10) // BX - branch with possible mode transfer
{
#ifdef ARM7_THUMB
- int Rn = ARM7.Rx[ARM7.kod & 0xf];
+ int Rn = cpu->Rx[cpu->kod & 0xf];
// switching to Thumb mode?
if (Rn & 1)
{
- ARM7_SetCPSR(ARM7.Rx[ARM7_CPSR] | ARM7_CPSR_T);
+ ARM7_SetCPSR(cpu->Rx[ARM7_CPSR] | ARM7_CPSR_T);
}
- ARM7.Rx[ARM7_PC] = Rn & ~1;
+ cpu->Rx[ARM7_PC] = Rn & ~1;
#endif
}
// 15 constant bits
- else if ((ARM7.kod & 0x0fb00ff0) == 0x01000090)
- R_SWP ();
+ else if ((cpu->kod & 0x0fb00ff0) == 0x01000090)
+ R_SWP (cpu);
// 10 constant bits
- else if ((ARM7.kod & 0x0fc000f0) == 0x00000090)
- R_MUL_MLA ();
+ else if ((cpu->kod & 0x0fc000f0) == 0x00000090)
+ R_MUL_MLA (cpu);
// 10 constant bits
- else if ((ARM7.kod & 0x0e400f90) == 0x00000090)
- R_HSDT ();
+ else if ((cpu->kod & 0x0e400f90) == 0x00000090)
+ R_HSDT (cpu);
// 9 constant bits
- else if ((ARM7.kod & 0x0f8000f0) == 0x00800090)
+ else if ((cpu->kod & 0x0f8000f0) == 0x00800090)
{
// logerror("G00x / Multiply long\n");
}
// 6 constant bits
- else if ((ARM7.kod & 0x0e400090) == 0x00400090)
- R_HSDT ();
+ else if ((cpu->kod & 0x0e400090) == 0x00400090)
+ R_HSDT (cpu);
// 2 constant bits
else
{
- if ((ARM7.kod & 0x01900000) == 0x01000000)
+ if ((cpu->kod & 0x01900000) == 0x01000000)
// TST, TEQ, CMP & CMN without S bit are "PSR Transfer"
- R_PSR ();
+ R_PSR (cpu);
else
// the rest is "Data processing"
- R_DP ();
+ R_DP (cpu);
}
#else
- if ((ARM7.kod & 0x03b00090) == 0x01000090)
- R_SWP ();
- else if ((ARM7.kod & 0x03c00090) == 0x00000090)
- R_MUL_MLA ();
+ if ((cpu->kod & 0x03b00090) == 0x01000090)
+ R_SWP (cpu);
+ else if ((cpu->kod & 0x03c00090) == 0x00000090)
+ R_MUL_MLA (cpu);
else
{
- if ((ARM7.kod & 0x01900000) == 0x01000000)
+ if ((cpu->kod & 0x01900000) == 0x01000000)
// TST, TEQ, CMP & CMN without S bit are "PSR Transfer"
- R_PSR ();
+ R_PSR (cpu);
else
// the rest is "Data processing"
- R_DP ();
+ R_DP (cpu);
}
#endif
}
@@ -576,33 +577,33 @@ void R_G00x ()
//--------------------------------------------------------------------------
/** Single data swap. */
-void R_SWP ()
+void R_SWP (struct sARM7 *cpu)
{
int Rn, Rd, Rm;
UINT32 adres, w;
-#define BIT_B (ARM7.kod & (1 << 21))
+#define BIT_B (cpu->kod & (1 << 21))
s_cykle += 4;
// none of these can be PC
- Rn = (ARM7.kod >> 16) & 15;
- Rd = (ARM7.kod >> 12) & 15;
- Rm = ARM7.kod & 15;
- adres = ARM7.Rx [Rn];
+ Rn = (cpu->kod >> 16) & 15;
+ Rd = (cpu->kod >> 12) & 15;
+ Rm = cpu->kod & 15;
+ adres = cpu->Rx [Rn];
if (BIT_B)
{
// "byte"
- w = arm7_read_8 (adres);
- arm7_write_8 (adres, (UINT8)ARM7.Rx [Rm]);
+ w = arm7_read_8 (cpu, adres);
+ arm7_write_8 (cpu, adres, (UINT8)cpu->Rx [Rm]);
}
else
{
// "word"
- w = RBOD (arm7_read_32 (adres & ~3), adres & 3);
- arm7_write_32 (adres & ~3, ARM7.Rx [Rm]);
+ w = RBOD (arm7_read_32 (cpu, adres & ~3), adres & 3);
+ arm7_write_32 (cpu, adres & ~3, cpu->Rx [Rm]);
}
- ARM7.Rx [Rd] = w;
+ cpu->Rx [Rd] = w;
#undef BIT_B
}
@@ -610,37 +611,37 @@ void R_SWP ()
//--------------------------------------------------------------------------
/** Multiply instructions. */
-void R_MUL_MLA ()
+void R_MUL_MLA (struct sARM7 *cpu)
{
int Rm, Rs, Rn, Rd;
UINT32 wynik;
-#define BIT_A (ARM7.kod & (1 << 21))
-#define BIT_S (ARM7.kod & (1 << 20))
+#define BIT_A (cpu->kod & (1 << 21))
+#define BIT_S (cpu->kod & (1 << 20))
s_cykle += 2;
// none of these can be PC, also Rd != Rm
- Rd = (ARM7.kod >> 16) & 15,
- Rs = (ARM7.kod >> 8) & 15,
- Rm = ARM7.kod & 15;
+ Rd = (cpu->kod >> 16) & 15,
+ Rs = (cpu->kod >> 8) & 15,
+ Rm = cpu->kod & 15;
// MUL
- wynik = ARM7.Rx [Rm] * ARM7.Rx [Rs];
+ wynik = cpu->Rx [Rm] * cpu->Rx [Rs];
if (BIT_A)
{
// MLA
- Rn = (ARM7.kod >> 12) & 15;
- wynik += ARM7.Rx [Rn];
+ Rn = (cpu->kod >> 12) & 15;
+ wynik += cpu->Rx [Rn];
}
- ARM7.Rx [Rd] = wynik;
+ cpu->Rx [Rd] = wynik;
if (BIT_S)
{
// V remains unchanged, C is undefined
- ARM7.Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z);
+ cpu->Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z);
if (wynik == 0)
- ARM7.Rx [ARM7_CPSR] |= ARM7_CPSR_Z;
- ARM7.Rx [ARM7_CPSR] |= wynik & 0x80000000;
+ cpu->Rx [ARM7_CPSR] |= ARM7_CPSR_Z;
+ cpu->Rx [ARM7_CPSR] |= wynik & 0x80000000;
}
#undef BIT_S
@@ -650,77 +651,77 @@ void R_MUL_MLA ()
//--------------------------------------------------------------------------
/** PSR Transfer. */
-void R_PSR ()
+void R_PSR (struct sARM7 *cpu)
{
int Rd, Rm;
UINT32 w, arg;
-#define BIT_I (ARM7.kod & (1 << 25))
-#define BIT_P (ARM7.kod & (1 << 22))
+#define BIT_I (cpu->kod & (1 << 25))
+#define BIT_P (cpu->kod & (1 << 22))
// none of the registers involved can be PC
- if (ARM7.kod & (1 << 21))
+ if (cpu->kod & (1 << 21))
{
// MSR
- Rm = ARM7.kod & 15;
+ Rm = cpu->kod & 15;
if (BIT_I)
// immediate (lower 12 bits)
- arg = ROR (ARM7.kod & 0xff, ((ARM7.kod >> 8) & 0xf) * 2);
+ arg = ROR (cpu->kod & 0xff, ((cpu->kod >> 8) & 0xf) * 2);
else
// register
- arg = ARM7.Rx [Rm];
+ arg = cpu->Rx [Rm];
// decode mask bits
if (BIT_P)
{
- w = ARM7.Rx [ARM7_SPSR];
- if (ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR]) > ARM7_CPSR_M_usr &&\
- ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR]) < ARM7_CPSR_M_sys)
+ w = cpu->Rx [ARM7_SPSR];
+ if (ARM7_CPSR_M (cpu->Rx [ARM7_CPSR]) > ARM7_CPSR_M_usr &&\
+ ARM7_CPSR_M (cpu->Rx [ARM7_CPSR]) < ARM7_CPSR_M_sys)
{
- if (ARM7.kod & (1 << 16))
+ if (cpu->kod & (1 << 16))
w = (w & 0xffffff00) | (arg & 0x000000ff);
- if (ARM7.kod & (1 << 17))
+ if (cpu->kod & (1 << 17))
w = (w & 0xffff00ff) | (arg & 0x0000ff00);
- if (ARM7.kod & (1 << 18))
+ if (cpu->kod & (1 << 18))
w = (w & 0xff00ffff) | (arg & 0x00ff0000);
- if (ARM7.kod & (1 << 19))
+ if (cpu->kod & (1 << 19))
// ARMv5E should have 0xf8000000 argument mask
w = (w & 0x00ffffff) | (arg & 0xf0000000);
}
// force valid mode
w |= 0x10;
- ARM7.Rx [ARM7_SPSR] = w;
+ cpu->Rx [ARM7_SPSR] = w;
}
else
{
- w = ARM7.Rx [ARM7_CPSR];
+ w = cpu->Rx [ARM7_CPSR];
// only flags can be changed in User mode
- if (ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR]) != ARM7_CPSR_M_usr)
+ if (ARM7_CPSR_M (cpu->Rx [ARM7_CPSR]) != ARM7_CPSR_M_usr)
{
- if (ARM7.kod & (1 << 16))
+ if (cpu->kod & (1 << 16))
w = (w & 0xffffff00) | (arg & 0x000000ff);
- if (ARM7.kod & (1 << 17))
+ if (cpu->kod & (1 << 17))
w = (w & 0xffff00ff) | (arg & 0x0000ff00);
- if (ARM7.kod & (1 << 18))
+ if (cpu->kod & (1 << 18))
w = (w & 0xff00ffff) | (arg & 0x00ff0000);
}
- if (ARM7.kod & (1 << 19))
+ if (cpu->kod & (1 << 19))
// ARMv5E should have 0xf8000000 argument mask
w = (w & 0x00ffffff) | (arg & 0xf0000000);
// force valid mode
w |= 0x10;
- ARM7_SetCPSR (w);
+ ARM7_SetCPSR (cpu, w);
}
}
else
{
// MRS
- Rd = (ARM7.kod >> 12) & 15;
+ Rd = (cpu->kod >> 12) & 15;
if (BIT_P)
- ARM7.Rx [Rd] = ARM7.Rx [ARM7_SPSR];
+ cpu->Rx [Rd] = cpu->Rx [ARM7_SPSR];
else
- ARM7.Rx [Rd] = ARM7.Rx [ARM7_CPSR];
+ cpu->Rx [Rd] = cpu->Rx [ARM7_CPSR];
}
#undef BIT_P
@@ -730,146 +731,146 @@ void R_PSR ()
//--------------------------------------------------------------------------
/** Data processing instructions. */
-void R_DP ()
+void R_DP (struct sARM7 *cpu)
{
int Rn;
ARM7_REG arg1, arg2, w;
-#define BIT_I (ARM7.kod & (1 << 25))
+#define BIT_I (cpu->kod & (1 << 25))
// Rn can be PC, so we need to account for that
- Rn = (ARM7.kod >> 16) & 15;
+ Rn = (cpu->kod >> 16) & 15;
if (BIT_I)
{
if (Rn != ARM7_PC)
- arg1 = ARM7.Rx [Rn];
+ arg1 = cpu->Rx [Rn];
else
- arg1 = (ARM7.Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT;
+ arg1 = (cpu->Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT;
// immediate in lowest 12 bits
- arg2 = ROR (ARM7.kod & 0xff, ((ARM7.kod >> 8) & 0xf) * 2);
+ arg2 = ROR (cpu->kod & 0xff, ((cpu->kod >> 8) & 0xf) * 2);
// preload carry out from C
- ARM7.carry = (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0;
+ cpu->carry = (cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0;
}
else
{
if (Rn != ARM7_PC)
- arg1 = ARM7.Rx [Rn];
+ arg1 = cpu->Rx [Rn];
else
// register or immediate shift?
- if (ARM7.kod & (1 << 4))
- arg1 = (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT;
+ if (cpu->kod & (1 << 4))
+ arg1 = (cpu->Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT;
else
- arg1 = (ARM7.Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT;
+ arg1 = (cpu->Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT;
// calculate in barrel shifter
- arg2 = WyliczPrzes ();
+ arg2 = WyliczPrzes (cpu);
}
// decode instruction type
- switch ((ARM7.kod >> 21) & 15)
+ switch ((cpu->kod >> 21) & 15)
{
case 0:
// AND
- R_WynikDP (arg1 & arg2);
+ R_WynikDP (cpu, arg1 & arg2);
break;
case 1:
// EOR
- R_WynikDP (arg1 ^ arg2);
+ R_WynikDP (cpu, arg1 ^ arg2);
break;
case 2:
// SUB
w = arg1 - arg2;
- ARM7.carry = SUBCARRY (arg1, arg2, w);
- ARM7.overflow = SUBOVERFLOW (arg1, arg2, w);
- R_WynikDP (w);
+ cpu->carry = SUBCARRY (arg1, arg2, w);
+ cpu->overflow = SUBOVERFLOW (arg1, arg2, w);
+ R_WynikDP (cpu, w);
break;
case 3:
// RSB
w = arg2 - arg1;
- ARM7.carry = SUBCARRY (arg2, arg1, w);
- ARM7.overflow = SUBOVERFLOW (arg2, arg1, w);
- R_WynikDP (w);
+ cpu->carry = SUBCARRY (arg2, arg1, w);
+ cpu->overflow = SUBOVERFLOW (arg2, arg1, w);
+ R_WynikDP (cpu, w);
break;
case 4:
// ADD
w = arg1 + arg2;
- ARM7.carry = ADDCARRY (arg1, arg2, w);
- ARM7.overflow = ADDOVERFLOW (arg1, arg2, w);
- R_WynikDP (w);
+ cpu->carry = ADDCARRY (arg1, arg2, w);
+ cpu->overflow = ADDOVERFLOW (arg1, arg2, w);
+ R_WynikDP (cpu, w);
break;
case 5:
// ADC
- w = arg1 + arg2 + ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0);
- ARM7.carry = ADDCARRY (arg1, arg2, w);
- ARM7.overflow = ADDOVERFLOW (arg1, arg2, w);
- R_WynikDP (w);
+ w = arg1 + arg2 + ((cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0);
+ cpu->carry = ADDCARRY (arg1, arg2, w);
+ cpu->overflow = ADDOVERFLOW (arg1, arg2, w);
+ R_WynikDP (cpu, w);
break;
case 6:
// SBC
- w = arg1 - arg2 - ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 0 : 1);
- ARM7.carry = SUBCARRY (arg1, arg2, w);
- ARM7.overflow = SUBOVERFLOW (arg1, arg2, w);
- R_WynikDP (w);
+ w = arg1 - arg2 - ((cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 0 : 1);
+ cpu->carry = SUBCARRY (arg1, arg2, w);
+ cpu->overflow = SUBOVERFLOW (arg1, arg2, w);
+ R_WynikDP (cpu, w);
break;
case 7:
// RSC
- w = arg2 - arg1 - ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 0 : 1);
- ARM7.carry = SUBCARRY (arg2, arg1, w);
- ARM7.overflow = SUBOVERFLOW (arg2, arg1, w);
- R_WynikDP (w);
+ w = arg2 - arg1 - ((cpu->Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 0 : 1);
+ cpu->carry = SUBCARRY (arg2, arg1, w);
+ cpu->overflow = SUBOVERFLOW (arg2, arg1, w);
+ R_WynikDP (cpu, w);
break;
case 8:
// TST
- R_FlagiDP (arg1 & arg2);
+ R_FlagiDP (cpu, arg1 & arg2);
break;
case 9:
// TEQ
- R_FlagiDP (arg1 ^ arg2);
+ R_FlagiDP (cpu, arg1 ^ arg2);
break;
case 10:
// CMP
w = arg1 - arg2;
- ARM7.carry = SUBCARRY (arg1, arg2, w);
- ARM7.overflow = SUBOVERFLOW (arg1, arg2, w);
- R_FlagiDP (w);
+ cpu->carry = SUBCARRY (arg1, arg2, w);
+ cpu->overflow = SUBOVERFLOW (arg1, arg2, w);
+ R_FlagiDP (cpu, w);
break;
case 11:
// CMN
w = arg1 + arg2;
- ARM7.carry = ADDCARRY (arg1, arg2, w);
- ARM7.overflow = ADDOVERFLOW (arg1, arg2, w);
- R_FlagiDP (w);
+ cpu->carry = ADDCARRY (arg1, arg2, w);
+ cpu->overflow = ADDOVERFLOW (arg1, arg2, w);
+ R_FlagiDP (cpu, w);
break;
case 12:
// ORR
- R_WynikDP (arg1 | arg2);
+ R_WynikDP (cpu, arg1 | arg2);
break;
case 13:
// MOV
- R_WynikDP (arg2);
+ R_WynikDP (cpu, arg2);
break;
case 14:
// BIC
- R_WynikDP (arg1 & ~arg2);
+ R_WynikDP (cpu, arg1 & ~arg2);
break;
case 15:
// MVN
- R_WynikDP (~arg2);
+ R_WynikDP (cpu, ~arg2);
break;
}
@@ -879,25 +880,25 @@ void R_DP ()
//--------------------------------------------------------------------------
/** Data processing result writeback. */
-void R_WynikDP (ARM7_REG w)
+void R_WynikDP (struct sARM7 *cpu, ARM7_REG w)
{
int Rd;
-#define BIT_S (ARM7.kod & (1 << 20))
+#define BIT_S (cpu->kod & (1 << 20))
- Rd = (ARM7.kod >> 12) & 15;
- ARM7.Rx [Rd] = w;
+ Rd = (cpu->kod >> 12) & 15;
+ cpu->Rx [Rd] = w;
if (BIT_S)
{
if (Rd == ARM7_PC)
{
s_cykle += 4;
// copy current SPSR to CPSR
- ARM7_SetCPSR (ARM7.Rx [ARM7_SPSR]);
+ ARM7_SetCPSR (cpu, cpu->Rx [ARM7_SPSR]);
}
else
// save new flags
- R_FlagiDP (w);
+ R_FlagiDP (cpu, w);
}
#undef BIT_S
@@ -906,62 +907,62 @@ void R_WynikDP (ARM7_REG w)
//--------------------------------------------------------------------------
/** Data processing flags writeback. */
-void R_FlagiDP (ARM7_REG w)
+void R_FlagiDP (struct sARM7 *cpu, ARM7_REG w)
{
// arithmetic or logical instruction?
- if (s_tabAL [(ARM7.kod >> 21) & 15])
+ if (s_tabAL [(cpu->kod >> 21) & 15])
{
- ARM7.Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_C |\
+ cpu->Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_C |\
ARM7_CPSR_V);
- ARM7.Rx [ARM7_CPSR] |= ARM7.overflow << 28;
+ cpu->Rx [ARM7_CPSR] |= cpu->overflow << 28;
}
else
- ARM7.Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_C);
- ARM7.Rx [ARM7_CPSR] |= ARM7.carry << 29;
+ cpu->Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_C);
+ cpu->Rx [ARM7_CPSR] |= cpu->carry << 29;
if (w == 0)
- ARM7.Rx [ARM7_CPSR] |= ARM7_CPSR_Z;
- ARM7.Rx [ARM7_CPSR] |= w & 0x80000000;
+ cpu->Rx [ARM7_CPSR] |= ARM7_CPSR_Z;
+ cpu->Rx [ARM7_CPSR] |= w & 0x80000000;
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Single data transfer. */
-void R_SDT (void)
+void R_SDT (struct sARM7 *cpu)
{
int Rn, Rd, offset;
UINT32 adres, w = 0;
-#define BIT_I (ARM7.kod & (1 << 25))
-#define BIT_P (ARM7.kod & (1 << 24))
-#define BIT_U (ARM7.kod & (1 << 23))
-#define BIT_B (ARM7.kod & (1 << 22))
-#define BIT_W (ARM7.kod & (1 << 21))
-#define BIT_L (ARM7.kod & (1 << 20))
+#define BIT_I (cpu->kod & (1 << 25))
+#define BIT_P (cpu->kod & (1 << 24))
+#define BIT_U (cpu->kod & (1 << 23))
+#define BIT_B (cpu->kod & (1 << 22))
+#define BIT_W (cpu->kod & (1 << 21))
+#define BIT_L (cpu->kod & (1 << 20))
- if (BIT_I && (ARM7.kod & (1 << 4)))
+ if (BIT_I && (cpu->kod & (1 << 4)))
{
- R_Und ();
+ R_Und (cpu);
return;
}
- Rn = (ARM7.kod >> 16) & 15,
- Rd = (ARM7.kod >> 12) & 15;
+ Rn = (cpu->kod >> 16) & 15,
+ Rd = (cpu->kod >> 12) & 15;
if (Rn != ARM7_PC)
- adres = ARM7.Rx [Rn];
+ adres = cpu->Rx [Rn];
else
- adres = ARM7.Rx [ARM7_PC] & ~3;
+ adres = cpu->Rx [ARM7_PC] & ~3;
if (!BIT_L)
if (Rd != ARM7_PC)
- w = ARM7.Rx [Rd];
+ w = cpu->Rx [Rd];
else
- w = (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT;
+ w = (cpu->Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT;
if (BIT_I)
// calculate value in barrel shifter
- offset = WyliczPrzes ();
+ offset = WyliczPrzes (cpu);
else
// immediate in lowest 12 bits
- offset = ARM7.kod & 0xfff;
+ offset = cpu->kod & 0xfff;
if (!BIT_U)
offset = -offset;
@@ -971,11 +972,11 @@ void R_SDT (void)
adres += offset;
if (BIT_W)
// "write-back"
- ARM7.Rx [Rn] = adres;
+ cpu->Rx [Rn] = adres;
}
else
// "post-index"
- ARM7.Rx [Rn] += offset;
+ cpu->Rx [Rn] += offset;
if (Rn == ARM7_PC)
adres += 8 + PC_ADJUSTMENT;
@@ -985,10 +986,10 @@ void R_SDT (void)
// "load"
if (BIT_B)
// "byte"
- ARM7.Rx [Rd] = arm7_read_8 (adres);
+ cpu->Rx [Rd] = arm7_read_8 (cpu, adres);
else
// "word"
- ARM7.Rx [Rd] = RBOD (arm7_read_32 (adres & ~3), adres & 3);
+ cpu->Rx [Rd] = RBOD (arm7_read_32 (cpu, adres & ~3), adres & 3);
}
else
{
@@ -996,10 +997,10 @@ void R_SDT (void)
// "store"
if (BIT_B)
// "byte"
- arm7_write_8 (adres, (UINT8)w);
+ arm7_write_8 (cpu, adres, (UINT8)w);
else
// "word"
- arm7_write_32 (adres & ~3, w);
+ arm7_write_32 (cpu, adres & ~3, w);
}
#undef BIT_L
@@ -1013,69 +1014,69 @@ void R_SDT (void)
//--------------------------------------------------------------------------
/** Undefined. */
-void R_Und ()
+void R_Und (struct sARM7 *cpu)
{
- UINT32 sr = ARM7.Rx [ARM7_CPSR];
- ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_und) | ARM7_CPSR_I);
- ARM7.Rx [ARM7_SPSR] = sr;
- ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC] + 4;
- ARM7.Rx [ARM7_PC] = 0x00000004;
+ UINT32 sr = cpu->Rx [ARM7_CPSR];
+ ARM7_SetCPSR (cpu, ARM7_CPSR_MX (sr, ARM7_CPSR_M_und) | ARM7_CPSR_I);
+ cpu->Rx [ARM7_SPSR] = sr;
+ cpu->Rx [ARM7_LR] = cpu->Rx [ARM7_PC] + 4;
+ cpu->Rx [ARM7_PC] = 0x00000004;
}
//--------------------------------------------------------------------------
-#define BIT_U (ARM7.kod & (1 << 23))
-#define BIT_S (ARM7.kod & (1 << 22))
+#define BIT_U (cpu->kod & (1 << 23))
+#define BIT_S (cpu->kod & (1 << 22))
//--------------------------------------------------------------------------
/** Block Data Transfer. */
-void R_BDT ()
+void R_BDT (struct sARM7 *cpu)
{
int Rn, usr = FALSE;
UINT32 adres;
ARM7_REG cpsr = 0;
-#define BIT_L (ARM7.kod & (1 << 20))
+#define BIT_L (cpu->kod & (1 << 20))
// Rn can't be PC
- Rn = (ARM7.kod >> 16) & 15;
- adres = ARM7.Rx [Rn];
+ Rn = (cpu->kod >> 16) & 15;
+ adres = cpu->Rx [Rn];
// transfer in User mode
if (BIT_S)
- if (!BIT_L || !(ARM7.kod & (1 << ARM7_PC)))
+ if (!BIT_L || !(cpu->kod & (1 << ARM7_PC)))
usr = TRUE;
if (usr)
{
//EMU_BLAD (BLAD_WEWNETRZNY, "BDT: user transfer");
- cpsr = ARM7.Rx [ARM7_CPSR];
- ARM7_SetCPSR (ARM7_CPSR_MX (cpsr, ARM7_CPSR_M_usr));
+ cpsr = cpu->Rx [ARM7_CPSR];
+ ARM7_SetCPSR (cpu, ARM7_CPSR_MX (cpsr, ARM7_CPSR_M_usr));
}
if (BIT_L)
// "load"
- R_LDM (Rn, adres);
+ R_LDM (cpu, Rn, adres);
else
// "store"
- R_STM (Rn, adres);
+ R_STM (cpu, Rn, adres);
if (usr)
- ARM7_SetCPSR (cpsr);
+ ARM7_SetCPSR (cpu, cpsr);
#undef BIT_L
}
//--------------------------------------------------------------------------
-#define BIT_P (ARM7.kod & (1 << 24))
-#define BIT_W (ARM7.kod & (1 << 21))
+#define BIT_P (cpu->kod & (1 << 24))
+#define BIT_W (cpu->kod & (1 << 21))
//--------------------------------------------------------------------------
/** Block load instructions. */
-void R_LDM (int Rn, UINT32 adres)
+void R_LDM (struct sARM7 *cpu, int Rn, UINT32 adres)
{
int i, n, sp;
// count registers on the list
for (i = 0, n = 0; i < 16; i++)
- if (ARM7.kod & (1 << i))
+ if (cpu->kod & (1 << i))
n++;
s_cykle += n * 2 + 1;
@@ -1091,41 +1092,41 @@ void R_LDM (int Rn, UINT32 adres)
}
if (BIT_W)
// "write-back"
- ARM7.Rx [Rn] += n;
+ cpu->Rx [Rn] += n;
// for all registers in mask
if (sp)
for (i = 0; i < 16; i++)
{
- if (!(ARM7.kod & (1 << i)))
+ if (!(cpu->kod & (1 << i)))
continue;
adres += 4;
- ARM7.Rx [i] = arm7_read_32 (adres);
+ cpu->Rx [i] = arm7_read_32 (cpu, adres);
}
else
for (i = 0; i < 16; i++)
{
- if (!(ARM7.kod & (1 << i)))
+ if (!(cpu->kod & (1 << i)))
continue;
- ARM7.Rx [i] = arm7_read_32 (adres);
+ cpu->Rx [i] = arm7_read_32 (cpu, adres);
adres += 4;
}
// special case - mode change when PC is written
- if ((ARM7.kod & (1 << ARM7_PC)) && BIT_S)
- ARM7_SetCPSR (ARM7.Rx [ARM7_SPSR]);
+ if ((cpu->kod & (1 << ARM7_PC)) && BIT_S)
+ ARM7_SetCPSR (cpu, cpu->Rx [ARM7_SPSR]);
}
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/** Block store instructions. */
-void R_STM (int Rn, UINT32 adres)
+void R_STM (struct sARM7 *cpu, int Rn, UINT32 adres)
{
int i, n, p, sp;
// count registers on the list and remember the first one
for (i = 0, n = 0, p = -1; i < 16; i++)
- if (ARM7.kod & (1 << i))
+ if (cpu->kod & (1 << i))
{
n++;
if (p < 0)
@@ -1146,37 +1147,37 @@ void R_STM (int Rn, UINT32 adres)
// if base register is not the first one to transfer, writeback happens here
if (BIT_W && Rn != p)
// "write-back"
- ARM7.Rx [Rn] += n;
+ cpu->Rx [Rn] += n;
// registers R0-R14
if (sp)
for (i = 0; i < 15; i++)
{
- if (!(ARM7.kod & (1 << i)))
+ if (!(cpu->kod & (1 << i)))
continue;
adres += 4;
- arm7_write_32 (adres, ARM7.Rx [i]);
+ arm7_write_32 (cpu, adres, cpu->Rx [i]);
}
else
for (i = 0; i < 15; i++)
{
- if (!(ARM7.kod & (1 << i)))
+ if (!(cpu->kod & (1 << i)))
continue;
- arm7_write_32 (adres, ARM7.Rx [i]);
+ arm7_write_32 (cpu, adres, cpu->Rx [i]);
adres += 4;
}
// PC is a special case
- if (ARM7.kod & (1 << ARM7_PC))
+ if (cpu->kod & (1 << ARM7_PC))
{
if (sp)
{
adres += 4;
- arm7_write_32 (adres, (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT);
+ arm7_write_32 (cpu, adres, (cpu->Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT);
}
else
{
- arm7_write_32 (adres, (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT);
+ arm7_write_32 (cpu, adres, (cpu->Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT);
adres += 4;
}
}
@@ -1184,7 +1185,7 @@ void R_STM (int Rn, UINT32 adres)
// if base register is the first one to transfer, writeback happens here
if (BIT_W && Rn == p)
// "write-back"
- ARM7.Rx [Rn] += n;
+ cpu->Rx [Rn] += n;
}
//--------------------------------------------------------------------------
#undef BIT_W
@@ -1194,22 +1195,22 @@ void R_STM (int Rn, UINT32 adres)
//--------------------------------------------------------------------------
/** Branch/Branch with link. */
-void R_B_BL ()
+void R_B_BL (struct sARM7 *cpu)
{
INT32 offset;
-#define BIT_L (ARM7.kod & (1 << 24))
+#define BIT_L (cpu->kod & (1 << 24))
s_cykle += 4;
- offset = (ARM7.kod & 0x00ffffff) << 2;
+ offset = (cpu->kod & 0x00ffffff) << 2;
if (offset & 0x02000000)
offset |= 0xfc000000;
offset += 8 + PC_ADJUSTMENT;
if (BIT_L)
// "Branch with link"
- ARM7.Rx [ARM7_LR] = (ARM7.Rx [ARM7_PC] & ~3) + 4 + PC_ADJUSTMENT;
+ cpu->Rx [ARM7_LR] = (cpu->Rx [ARM7_PC] & ~3) + 4 + PC_ADJUSTMENT;
// "Branch"
- ARM7.Rx [ARM7_PC] += offset;
+ cpu->Rx [ARM7_PC] += offset;
#undef BIT_L
}
@@ -1217,7 +1218,7 @@ void R_B_BL ()
//--------------------------------------------------------------------------
/** Group 110 opcodes. */
-void R_G110 ()
+void R_G110 (struct sARM7 *cpu)
{
// logerror("ARM7: G110 / Coprocessor data transfer\n");
}
@@ -1225,22 +1226,22 @@ void R_G110 ()
//--------------------------------------------------------------------------
/** Group 111 opcodes. */
-void R_G111 ()
+void R_G111 (struct sARM7 *cpu)
{
- if ((ARM7.kod & 0xf0000000) == 0xe0000000)
+ if ((cpu->kod & 0xf0000000) == 0xe0000000)
{
-/* if (ARM7.kod & (1 << 4))
+/* if (cpu->kod & (1 << 4))
logerror("ARM7: G111 / Coprocessor register transfer\n");
else
logerror("ARM7: G111 / Coprocessor data operation\n"); */
}
else
{
- UINT32 sr = ARM7.Rx [ARM7_CPSR];
- ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_svc) | ARM7_CPSR_I);
- ARM7.Rx [ARM7_SPSR] = sr;
- ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC];
- ARM7.Rx [ARM7_PC] = 0x00000008;
+ UINT32 sr = cpu->Rx [ARM7_CPSR];
+ ARM7_SetCPSR (cpu, ARM7_CPSR_MX (sr, ARM7_CPSR_M_svc) | ARM7_CPSR_I);
+ cpu->Rx [ARM7_SPSR] = sr;
+ cpu->Rx [ARM7_LR] = cpu->Rx [ARM7_PC];
+ cpu->Rx [ARM7_PC] = 0x00000008;
}
}
//--------------------------------------------------------------------------
@@ -1253,34 +1254,34 @@ void R_HSDT ()
int Rm, Rd, Rn, offset;
uint32_t adres, w;
-#define BIT_P (ARM7.kod & (1 << 24))
-#define BIT_U (ARM7.kod & (1 << 23))
-#define BIT_W (ARM7.kod & (1 << 21))
-#define BIT_L (ARM7.kod & (1 << 20))
-#define BIT_S (ARM7.kod & (1 << 6))
-#define BIT_H (ARM7.kod & (1 << 5))
+#define BIT_P (cpu->kod & (1 << 24))
+#define BIT_U (cpu->kod & (1 << 23))
+#define BIT_W (cpu->kod & (1 << 21))
+#define BIT_L (cpu->kod & (1 << 20))
+#define BIT_S (cpu->kod & (1 << 6))
+#define BIT_H (cpu->kod & (1 << 5))
// Rm can't be PC
- Rn = (ARM7.kod >> 16) & 15;
- Rd = (ARM7.kod >> 12) & 15;
+ Rn = (cpu->kod >> 16) & 15;
+ Rd = (cpu->kod >> 12) & 15;
if (Rn != ARM7_PC)
- adres = ARM7.Rx [Rn];
+ adres = cpu->Rx [Rn];
else
- adres = ARM7.Rx [ARM7_PC] & ~3;
+ adres = cpu->Rx [ARM7_PC] & ~3;
if (!BIT_L)
if (Rd != ARM7_PC)
- w = ARM7.Rx [Rd];
+ w = cpu->Rx [Rd];
else
- w = (ARM7.Rx [ARM7_PC] & ~3) + 12 + POPRAWKA_PC;
+ w = (cpu->Rx [ARM7_PC] & ~3) + 12 + POPRAWKA_PC;
if (1 << 22)
// immediate
- offset = ((ARM7.kod >> 4) & 0xf0) | (ARM7.kod & 15);
+ offset = ((cpu->kod >> 4) & 0xf0) | (cpu->kod & 15);
else
{
// register
- Rm = ARM7.kod & 15;
- offset = ARM7.Rx [Rm];
+ Rm = cpu->kod & 15;
+ offset = cpu->Rx [Rm];
}
if (!BIT_U)
@@ -1291,11 +1292,11 @@ void R_HSDT ()
adres += offset;
if (BIT_W)
// "write-back"
- ARM7.Rx [Rn] = adres;
+ cpu->Rx [Rn] = adres;
}
else
// "post-index"
- ARM7.Rx [Rn] += offset;
+ cpu->Rx [Rn] += offset;
if (Rn == ARM7_PC)
adres += 8 + POPRAWKA_PC;
@@ -1307,14 +1308,14 @@ void R_HSDT ()
{
if (BIT_H)
// "signed halfword"
- ARM7.Rx [Rd] = (INT32)(INT16)arm7_read_16 (adres);
+ cpu->Rx [Rd] = (INT32)(INT16)arm7_read_16 (adres);
else
// "signed byte"
- ARM7.Rx [Rd] = (INT32)(INT8)arm7_read_8 (adres);
+ cpu->Rx [Rd] = (INT32)(INT8)arm7_read_8 (cpu, adres);
}
else
// "unsigned halfword"
- ARM7.Rx [Rd] = arm7_read_16 (adres);
+ cpu->Rx [Rd] = arm7_read_16 (adres);
}
else
{
@@ -1325,7 +1326,7 @@ void R_HSDT ()
arm7_write_16 (adres, (UINT16)w);
else
// "byte"
- arm7_write_8 (adres, (UINT8)w);
+ arm7_write_8 (cpu, adres, (UINT8)w);
}
#undef BIT_H
diff --git a/plugins/ao/eng_dsf/arm7i.h b/plugins/ao/eng_dsf/arm7i.h
index 5a2e611b..9ca50188 100644
--- a/plugins/ao/eng_dsf/arm7i.h
+++ b/plugins/ao/eng_dsf/arm7i.h
@@ -13,7 +13,7 @@
// public functions
/** Single step, returns number of burned cycles. */
-int ARM7i_Step(void);
+int ARM7i_Step(struct sARM7 *cpu);
//--------------------------------------------------------------------------
#endif
diff --git a/plugins/ao/eng_dsf/arm7memil.c b/plugins/ao/eng_dsf/arm7memil.c
index b9daed83..c1872a2c 100644
--- a/plugins/ao/eng_dsf/arm7memil.c
+++ b/plugins/ao/eng_dsf/arm7memil.c
@@ -1,45 +1,45 @@
// memory inline functions shared by ARM and THUMB modes
-static INLINE void arm7_write_32(UINT32 addr, UINT32 data )
+static INLINE void arm7_write_32(struct sARM7 *cpu, UINT32 addr, UINT32 data )
{
addr &= ~3;
- dc_write32(addr,data);
+ dc_write32(cpu, addr,data);
}
-static INLINE void arm7_write_16(UINT32 addr, UINT16 data)
+static INLINE void arm7_write_16(struct sARM7 *cpu, UINT32 addr, UINT16 data)
{
addr &= ~1;
- dc_write16(addr,data);
+ dc_write16(cpu, addr,data);
}
-static INLINE void arm7_write_8(UINT32 addr, UINT8 data)
+static INLINE void arm7_write_8(struct sARM7 *cpu, UINT32 addr, UINT8 data)
{
- dc_write8(addr,data);
+ dc_write8(cpu, addr,data);
}
-static INLINE UINT32 arm7_read_32(UINT32 addr)
+static INLINE UINT32 arm7_read_32(struct sARM7 *cpu, UINT32 addr)
{
UINT32 result;
int k = (addr & 3) << 3;
if (k)
{
- result = dc_read32 (addr & ~3);
+ result = dc_read32 (cpu, addr & ~3);
result = (result >> k) | (result << (32 - k));
}
else
{
- result = dc_read32(addr);
+ result = dc_read32(cpu, addr);
}
return result;
}
-static INLINE UINT16 arm7_read_16(UINT32 addr)
+static INLINE UINT16 arm7_read_16(struct sARM7 *cpu, UINT32 addr)
{
UINT16 result;
- result = dc_read16(addr & ~1);
+ result = dc_read16(cpu, addr & ~1);
if (addr & 1)
{
@@ -49,8 +49,8 @@ static INLINE UINT16 arm7_read_16(UINT32 addr)
return result;
}
-static INLINE UINT8 arm7_read_8(UINT32 addr)
+static INLINE UINT8 arm7_read_8(struct sARM7 *cpu, UINT32 addr)
{
- return dc_read8(addr);
+ return dc_read8(cpu, addr);
}
diff --git a/plugins/ao/eng_dsf/dc_hw.c b/plugins/ao/eng_dsf/dc_hw.c
index d6b10548..d0dc87fd 100644
--- a/plugins/ao/eng_dsf/dc_hw.c
+++ b/plugins/ao/eng_dsf/dc_hw.c
@@ -12,14 +12,12 @@
#include "arm7core.h"
#endif
-uint8 dc_ram[8*1024*1024];
-
-static void aica_irq(int irq)
+static void aica_irq(struct sARM7 *cpu, int irq)
{
if (irq > 0)
{
#if DK_CORE
- ARM7_SetFIQ(TRUE);
+ ARM7_SetFIQ(cpu, TRUE);
#else
set_irq_line(ARM7_FIRQ_LINE, 1);
#endif
@@ -27,7 +25,7 @@ static void aica_irq(int irq)
else
{
#if DK_CORE
- ARM7_SetFIQ(FALSE);
+ ARM7_SetFIQ(cpu, FALSE);
#else
set_irq_line(ARM7_FIRQ_LINE, 0);
#endif
@@ -39,19 +37,11 @@ static void aica_irq(int irq)
#define MIXER(level,pan) ((level & 0xff) | ((pan & 0x03) << 8))
#define YM3012_VOL(LVol,LPan,RVol,RPan) (MIXER(LVol,LPan)|(MIXER(RVol,RPan) << 16))
-static struct AICAinterface aica_interface =
-{
- 1,
- { dc_ram, },
- { YM3012_VOL(100, MIXER_PAN_LEFT, 100, MIXER_PAN_RIGHT) },
- { aica_irq, },
-};
-
-uint8 dc_read8(int addr)
+uint8 dc_read8(struct sARM7 *cpu, int addr)
{
if (addr < 0x800000)
{
- return dc_ram[addr];
+ return cpu->dc_ram[addr];
}
if ((addr >= 0x800000) && (addr <= 0x807fff))
@@ -72,11 +62,11 @@ uint8 dc_read8(int addr)
return -1;
}
-uint16 dc_read16(int addr)
+uint16 dc_read16(struct sARM7 *cpu, int addr)
{
if (addr < 0x800000)
{
- return dc_ram[addr] | (dc_ram[addr+1]<<8);
+ return cpu->dc_ram[addr] | (cpu->dc_ram[addr+1]<<8);
}
if ((addr >= 0x800000) && (addr <= 0x807fff))
@@ -88,11 +78,11 @@ uint16 dc_read16(int addr)
return -1;
}
-uint32 dc_read32(int addr)
+uint32 dc_read32(struct sARM7 *cpu, int addr)
{
if (addr < 0x800000)
{
- return dc_ram[addr] | (dc_ram[addr+1]<<8) | (dc_ram[addr+2]<<16) | (dc_ram[addr+3]<<24);
+ return cpu->dc_ram[addr] | (cpu->dc_ram[addr+1]<<8) | (cpu->dc_ram[addr+2]<<16) | (cpu->dc_ram[addr+3]<<24);
}
if ((addr >= 0x800000) && (addr <= 0x807fff))
@@ -105,11 +95,11 @@ uint32 dc_read32(int addr)
return 0;
}
-void dc_write8(int addr, uint8 data)
+void dc_write8(struct sARM7 *cpu, int addr, uint8 data)
{
if (addr < 0x800000)
{
- dc_ram[addr] = data;
+ cpu->dc_ram[addr] = data;
return;
}
@@ -126,12 +116,12 @@ void dc_write8(int addr, uint8 data)
printf("W8 %x @ %x\n", data, addr);
}
-void dc_write16(int addr, uint16 data)
+void dc_write16(struct sARM7 *cpu, int addr, uint16 data)
{
if (addr < 0x800000)
{
- dc_ram[addr] = data&0xff;
- dc_ram[addr+1] = (data>>8) & 0xff;
+ cpu->dc_ram[addr] = data&0xff;
+ cpu->dc_ram[addr+1] = (data>>8) & 0xff;
return;
}
@@ -144,14 +134,14 @@ void dc_write16(int addr, uint16 data)
printf("W16 %x @ %x\n", data, addr);
}
-void dc_write32(int addr, uint32 data)
+void dc_write32(struct sARM7 *cpu, int addr, uint32 data)
{
if (addr < 0x800000)
{
- dc_ram[addr] = data&0xff;
- dc_ram[addr+1] = (data>>8) & 0xff;
- dc_ram[addr+2] = (data>>16) & 0xff;
- dc_ram[addr+3] = (data>>24) & 0xff;
+ cpu->dc_ram[addr] = data&0xff;
+ cpu->dc_ram[addr+1] = (data>>8) & 0xff;
+ cpu->dc_ram[addr+2] = (data>>16) & 0xff;
+ cpu->dc_ram[addr+3] = (data>>24) & 0xff;
return;
}
@@ -166,9 +156,23 @@ void dc_write32(int addr, uint32 data)
printf("W32 %x @ %x\n", data, addr);
}
-void dc_hw_init(void)
+void dc_hw_init(struct sARM7 *cpu)
+{
+#if 0
+static struct AICAinterface aica_interface =
{
- aica_interface.region[0] = dc_ram;
- aica_start(&aica_interface);
+ 1,
+ { cpu->dc_ram, },
+ { YM3012_VOL(100, MIXER_PAN_LEFT, 100, MIXER_PAN_RIGHT) },
+ { aica_irq, },
+};
+#endif
+
+ cpu->aica_interface.num = 1;
+ cpu->aica_interface.region[0] = cpu->dc_ram;
+ cpu->aica_interface.mixing_level[0] = YM3012_VOL(100, MIXER_PAN_LEFT, 100, MIXER_PAN_RIGHT);
+ cpu->aica_interface.irq_callback[0] = aica_irq;
+ cpu->aica_interface.cpu = cpu;
+ aica_start(&cpu->aica_interface);
}
diff --git a/plugins/ao/eng_dsf/dc_hw.h b/plugins/ao/eng_dsf/dc_hw.h
index b17de9e1..3b467f25 100644
--- a/plugins/ao/eng_dsf/dc_hw.h
+++ b/plugins/ao/eng_dsf/dc_hw.h
@@ -1,9 +1,15 @@
#ifndef _DC_HW_H_
#define _DC_HW_H_
-extern uint8 dc_ram[8*1024*1024];
-
-void dc_hw_init(void);
+#include "arm7i.h"
+
+void dc_hw_init(struct sARM7 *cpu);
+void dc_write8(struct sARM7 *cpu, int addr, uint8 data);
+void dc_write16(struct sARM7 *cpu, int addr, uint16 data);
+void dc_write32(struct sARM7 *cpu, int addr, uint32 data);
+uint8 dc_read8(struct sARM7 *cpu, int addr);
+uint16 dc_read16(struct sARM7 *cpu, int addr);
+uint32 dc_read32(struct sARM7 *cpu, int addr);
#endif
diff --git a/plugins/ao/eng_dsf/eng_dsf.c b/plugins/ao/eng_dsf/eng_dsf.c
index aa636def..e0edb383 100644
--- a/plugins/ao/eng_dsf/eng_dsf.c
+++ b/plugins/ao/eng_dsf/eng_dsf.c
@@ -19,7 +19,7 @@
#include "dc_hw.h"
#include "aica.h"
-#define DEBUG_LOADER (0)
+#define DEBUG_LOADER (1)
#define DK_CORE (1)
#if DK_CORE
@@ -32,12 +32,13 @@ typedef struct {
corlett_t *c;
char psfby[256];
uint32 decaybegin, decayend, total_samples;
+ struct sARM7 *cpu;
} dsf_synth_t;
-void *aica_start(const void *config);
+//void *aica_start(const void *config);
void AICA_Update(void *param, INT16 **inputs, INT16 **buf, int samples);
-void *dsf_start(uint8 *buffer, uint32 length)
+void *dsf_start(const char *path, uint8 *buffer, uint32 length)
{
dsf_synth_t *s = malloc (sizeof (dsf_synth_t));
memset (s, 0, sizeof (dsf_synth_t));
@@ -49,9 +50,6 @@ void *dsf_start(uint8 *buffer, uint32 length)
char *libfile;
int i;
- // clear Dreamcast work RAM before we start scribbling in it
- memset(dc_ram, 0, 8*1024*1024);
-
// Decode the current SSF
if (corlett_decode(buffer, length, &file, &file_len, &s->c) != AO_SUCCESS)
{
@@ -63,17 +61,32 @@ void *dsf_start(uint8 *buffer, uint32 length)
printf("%d bytes decoded\n", file_len);
#endif
+ s->cpu = ARM7_Alloc ();
// Get the library file, if any
for (i=0; i<9; i++) {
libfile = i ? s->c->libaux[i-1] : s->c->lib;
if (libfile[0] != 0)
{
uint64 tmp_length;
+ char libpath[PATH_MAX];
+ const char *e = path + strlen(path);
+ while (e > path && *e != '/') {
+ e--;
+ }
+ if (*e == '/') {
+ e++;
+ memcpy (libpath, path, e-path);
+ libpath[e-path] = 0;
+ strcat (libpath, libfile);
+ }
+ else {
+ strcpy (libpath, libfile);
+ }
#if DEBUG_LOADER
- printf("Loading library: %s\n", c->lib);
+ printf("Loading library: %s\n", libpath);
#endif
- if (ao_get_lib(libfile, &lib_raw_file, &tmp_length) != AO_SUCCESS)
+ if (ao_get_lib(libpath, &lib_raw_file, &tmp_length) != AO_SUCCESS)
{
dsf_stop (s);
return NULL;
@@ -92,7 +105,7 @@ void *dsf_start(uint8 *buffer, uint32 length)
// patch the file into ram
offset = lib_decoded[0] | lib_decoded[1]<<8 | lib_decoded[2]<<16 | lib_decoded[3]<<24;
- memcpy(&dc_ram[offset], lib_decoded+4, lib_len-4);
+ memcpy(&s->cpu->dc_ram[offset], lib_decoded+4, lib_len-4);
// Dispose the corlett structure for the lib - we don't use it
free(lib);
@@ -101,7 +114,7 @@ void *dsf_start(uint8 *buffer, uint32 length)
// now patch the file into RAM over the libraries
offset = file[3]<<24 | file[2]<<16 | file[1]<<8 | file[0];
- memcpy(&dc_ram[offset], file+4, file_len-4);
+ memcpy(&s->cpu->dc_ram[offset], file+4, file_len-4);
free(file);
@@ -116,23 +129,23 @@ void *dsf_start(uint8 *buffer, uint32 length)
}
}
- #if DEBUG_LOADER && 1
+ #if DEBUG_LOADER && 0
{
FILE *f;
f = fopen("dcram.bin", "wb");
- fwrite(dc_ram, 2*1024*1024, 1, f);
+ fwrite(s->cpu->dc_ram, 2*1024*1024, 1, f);
fclose(f);
}
#endif
#if DK_CORE
- ARM7_Init();
+ ARM7_Init(s->cpu);
#else
- arm7_init(0, 45000000, NULL, NULL);
- arm7_reset();
+ arm7_init(cpu, 0, 45000000, NULL, NULL);
+ arm7_reset(s->cpu);
#endif
- dc_hw_init();
+ dc_hw_init(s->cpu);
// now figure out the time in samples for the length/fade
lengthMS = psfTimeToMS(s->c->inf_length);
@@ -174,9 +187,9 @@ int32 dsf_gen(void *handle, int16 *buffer, uint32 samples)
for (i = 0; i < samples; i++)
{
#if DK_CORE
- ARM7_Execute((33000000 / 60 / 4) / 735);
+ ARM7_Execute(s->cpu, (33000000 / 60 / 4) / 735);
#else
- arm7_execute((33000000 / 60 / 4) / 735);
+ arm7_execute(s->cpu, (33000000 / 60 / 4) / 735);
#endif
stereo[0] = &output[opos];
stereo[1] = &output2[opos];
diff --git a/plugins/ao/eng_protos.h b/plugins/ao/eng_protos.h
index 4d01d4b2..9f4a02a1 100644
--- a/plugins/ao/eng_protos.h
+++ b/plugins/ao/eng_protos.h
@@ -9,31 +9,31 @@
// eng_protos.h
//
-void *psf_start(uint8 *, uint32 length);
+void *psf_start(const char *path, uint8 *, uint32 length);
int32 psf_gen(void *, int16 *, uint32);
int32 psf_stop(void *);
int32 psf_command(void *, int32, int32);
int32 psf_fill_info(void *, ao_display_info *);
-void *psf2_start(uint8 *, uint32 length);
+void *psf2_start(const char *path, uint8 *, uint32 length);
int32 psf2_gen(void *, int16 *, uint32);
int32 psf2_stop(void *);
int32 psf2_command(void *, int32, int32);
int32 psf2_fill_info(void *, ao_display_info *);
-void *qsf_start(uint8 *, uint32 length);
+void *qsf_start(const char *path, uint8 *, uint32 length);
int32 qsf_gen(void *, int16 *, uint32);
int32 qsf_stop(void *);
int32 qsf_command(void *, int32, int32);
int32 qsf_fill_info(void*, ao_display_info *);
-void *ssf_start(uint8 *, uint32 length);
+void *ssf_start(const char *path, uint8 *, uint32 length);
int32 ssf_gen(void *, int16 *, uint32);
int32 ssf_stop(void *);
int32 ssf_command(void *, int32, int32);
int32 ssf_fill_info(void *, ao_display_info *);
-void *spu_start(uint8 *, uint32 length);
+void *spu_start(const char *path, uint8 *, uint32 length);
int32 spu_gen(void *, int16 *, uint32);
int32 spu_stop(void *);
int32 spu_command(void *, int32, int32);
@@ -45,7 +45,7 @@ uint8 qsf_memory_readport(uint16 addr);
void qsf_memory_write(uint16 addr, uint8 byte);
void qsf_memory_writeport(uint16 addr, uint8 byte);
-void *dsf_start(uint8 *, uint32 length);
+void *dsf_start(const char *path, uint8 *, uint32 length);
int32 dsf_gen(void *, int16 *, uint32);
int32 dsf_stop(void *);
int32 dsf_command(void *, int32, int32);
diff --git a/plugins/ao/eng_psf/eng_psf.c b/plugins/ao/eng_psf/eng_psf.c
index 4b90e61c..86c1ac92 100644
--- a/plugins/ao/eng_psf/eng_psf.c
+++ b/plugins/ao/eng_psf/eng_psf.c
@@ -61,7 +61,7 @@ static void spu_update (unsigned char* pSound,long lBytes,void *data)
memcpy(s->spu_pOutput, pSound, lBytes);
}
-void *psf_start(uint8 *buffer, uint32 length)
+void *psf_start(const char *path, uint8 *buffer, uint32 length)
{
psf_synth_t *s = malloc (sizeof (psf_synth_t));
psf_refresh = -1;
diff --git a/plugins/ao/eng_psf/eng_psf2.c b/plugins/ao/eng_psf/eng_psf2.c
index 7ed1ac3a..854e9012 100644
--- a/plugins/ao/eng_psf/eng_psf2.c
+++ b/plugins/ao/eng_psf/eng_psf2.c
@@ -456,7 +456,7 @@ uint32 psf2_load_file(mips_cpu_context *cpu, char *file, uint8 *buf, uint32 bufl
return 0xffffffff;
}
-void *psf2_start(uint8 *buffer, uint32 length)
+void *psf2_start(const char *path, uint8 *buffer, uint32 length)
{
psf2_synth_t *s = malloc (sizeof (psf2_synth_t));
diff --git a/plugins/ao/eng_psf/eng_spu.c b/plugins/ao/eng_psf/eng_spu.c
index b13e0c5f..2adb9470 100644
--- a/plugins/ao/eng_psf/eng_spu.c
+++ b/plugins/ao/eng_psf/eng_spu.c
@@ -60,7 +60,7 @@ static void spu_update (unsigned char* pSound,long lBytes,void *data)
}
-void *spu_start(uint8 *buffer, uint32 length)
+void *spu_start(const char *path, uint8 *buffer, uint32 length)
{
spu_synth_t *s = malloc (sizeof (spu_synth_t));
memset (s, 0, sizeof (spu_synth_t));
diff --git a/plugins/ao/eng_qsf/eng_qsf.c b/plugins/ao/eng_qsf/eng_qsf.c
index a00b955a..3fc5e9a1 100644
--- a/plugins/ao/eng_qsf/eng_qsf.c
+++ b/plugins/ao/eng_qsf/eng_qsf.c
@@ -141,7 +141,7 @@ static int32 qsf_irq_cb(int param)
return 0x000000ff; // RST_38
}
-void *qsf_start(uint8 *buffer, uint32 length)
+void *qsf_start(const char *path, uint8 *buffer, uint32 length)
{
qsf_synth_t *s = malloc (sizeof (qsf_synth_t));
memset (s, 0, sizeof (qsf_synth_t));
diff --git a/plugins/ao/eng_ssf/eng_ssf.c b/plugins/ao/eng_ssf/eng_ssf.c
index 02d538ff..d3b63e2f 100644
--- a/plugins/ao/eng_ssf/eng_ssf.c
+++ b/plugins/ao/eng_ssf/eng_ssf.c
@@ -88,7 +88,7 @@ typedef struct {
void *scsp_start(const void *config);
void SCSP_Update(void *param, INT16 **inputs, INT16 **buf, int samples);
-void *ssf_start(uint8 *buffer, uint32 length)
+void *ssf_start(const char *path, uint8 *buffer, uint32 length)
{
ssf_synth_t *s = malloc (sizeof (ssf_synth_t));
memset (s, 0, sizeof (ssf_synth_t));
diff --git a/plugins/ao/main.c b/plugins/ao/main.c
index 58a765d5..ed6f8d60 100644
--- a/plugins/ao/main.c
+++ b/plugins/ao/main.c
@@ -41,7 +41,7 @@ static struct
{
uint32 sig;
char *name;
- void * (*start)(uint8 *, uint32); // returns handle
+ void * (*start)(const char *path, uint8 *, uint32); // returns handle
int32 (*gen)(void *handle, int16 *, uint32);
int32 (*stop)(void *handle);
int32 (*command)(void *handle, int32, int32);
@@ -196,7 +196,7 @@ int main(int argv, char *argc[])
return -1;
}
- void *handle = (*types[type].start)(buffer, size);
+ void *handle = (*types[type].start)(argc[1], buffer, size);
if (!handle)
{
@@ -260,9 +260,9 @@ ao_identify (char *buffer) {
}
void *
-ao_start (uint32 type, uint8 *buffer, uint32 size) {
+ao_start (uint32 type, const char *path, uint8 *buffer, uint32 size) {
printf ("ao_start %d %p %d\n", type, buffer, size);
- return (*types[type].start)(buffer, size);
+ return (*types[type].start)(path, buffer, size);
}
int
diff --git a/plugins/ao/plugin.c b/plugins/ao/plugin.c
index 6d648fad..36c5d2f7 100644
--- a/plugins/ao/plugin.c
+++ b/plugins/ao/plugin.c
@@ -90,7 +90,7 @@ aoplug_init (DB_fileinfo_t *_info, DB_playItem_t *it) {
return -1;
}
- info->decoder = ao_start (info->type, (uint8 *)info->filebuffer, info->filesize);
+ info->decoder = ao_start (info->type, it->fname, (uint8 *)info->filebuffer, info->filesize);
if (!info->decoder) {
fprintf (stderr, "psf: ao_start failed\n");
return -1;
@@ -184,7 +184,7 @@ aoplug_insert (DB_playItem_t *after, const char *fname) {
return NULL;
}
- void *dec = ao_start (type, (uint8*)buffer, size);
+ void *dec = ao_start (type, fname, (uint8*)buffer, size);
if (!dec) {
free (buffer);
return NULL;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 22:46:04 +0000