diff options
| author |  xleroy <xleroy@fca1b0fc-160b-0410-b1d3-a4f43f01ea2e> | 2011-08-05 12:04:58 +0000 |
|---|---|---|
| committer | xleroy <xleroy@fca1b0fc-160b-0410-b1d3-a4f43f01ea2e> | 2011-08-05 12:04:58 +0000 |
| commit | ab624a0ebf01a4f3e45aecb438e890b4da2f66f0 (patch) | |
| tree | ffac7325744b54d1973733cfa479e5fa2bc95eac /powerpc | |
| parent | 40a41ae1131f05269514e21f769d5d8c07c09c4a (diff) | |
More builtins for ARM and PowerPC
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1697 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
Diffstat (limited to 'powerpc')
| -rw-r--r-- | powerpc/CBuiltins.ml | 4 | ||||
| -rw-r--r-- | powerpc/PrintAsm.ml | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/powerpc/CBuiltins.ml b/powerpc/CBuiltins.ml index 4fbe6e4..6b68380 100644 --- a/powerpc/CBuiltins.ml +++ b/powerpc/CBuiltins.ml @@ -26,7 +26,9 @@ let builtins = { (TInt(IInt, []), [TInt(IInt, []); TInt(IInt, [])], false); "__builtin_mulhwu", (TInt(IUInt, []), [TInt(IUInt, []); TInt(IUInt, [])], false); - "__builtin_cntlzw", + "__builtin_cntlz", + (TInt(IUInt, []), [TInt(IUInt, [])], false); + "__builtin_bswap", (TInt(IUInt, []), [TInt(IUInt, [])], false); (* Float arithmetic *) "__builtin_fmadd", diff --git a/powerpc/PrintAsm.ml b/powerpc/PrintAsm.ml index 794441c..68e607b 100644 --- a/powerpc/PrintAsm.ml +++ b/powerpc/PrintAsm.ml @@ -428,8 +428,12 @@ let print_builtin_inline oc name args res = fprintf oc " mulhw %a, %a, %a\n" ireg res ireg a1 ireg a2 | "__builtin_mulhwu", [IR a1; IR a2], IR res -> fprintf oc " mulhwu %a, %a, %a\n" ireg res ireg a1 ireg a2 - | "__builtin_cntlzw", [IR a1], IR res -> + | "__builtin_cntlz", [IR a1], IR res -> fprintf oc " cntlzw %a, %a\n" ireg res ireg a1 + | "__builtin_bswap", [IR a1], IR res -> + fprintf oc " stwu %a, -8(%a)\n" ireg a1 ireg GPR1; + fprintf oc " lwbrx %a, %a, %a\n" ireg res ireg_or_zero GPR0 ireg GPR1; + fprintf oc " addi %a, %a, 8\n" ireg GPR1 ireg GPR1 (* Float arithmetic *) | "__builtin_fmadd", [FR a1; FR a2; FR a3], FR res -> fprintf oc " fmadd %a, %a, %a, %a\n" freg res freg a1 freg a2 freg a3 |