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| author |  xleroy <xleroy@fca1b0fc-160b-0410-b1d3-a4f43f01ea2e> | 2010-05-02 07:43:49 +0000 |
|---|---|---|
| committer | xleroy <xleroy@fca1b0fc-160b-0410-b1d3-a4f43f01ea2e> | 2010-05-02 07:43:49 +0000 |
| commit | 0cb770c9d2dcad16afdd8129558e356f31202803 (patch) | |
| tree | 4032dbc9c3f7e4bb80df2f7f681ca7bd5496e76e /powerpc | |
| parent | 3fb4ee15ed74c55923fe702a130d77120a471ca3 (diff) | |
In compilation of Sassign, avoid systematic move from a fresh temp.
Those moves are not always coalesced during coloring. The resulting
smaller RTL code also reduces the load on the rest of the back-end.
RTLgenspec.v: use spiffy saturateTrans tactic to speed up proof search.
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1330 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
Diffstat (limited to 'powerpc')
0 files changed, 0 insertions, 0 deletions