Updated ARM backend wrt new static analyses and optimizations.

NeedOp, Deadcode: must have distinct needs per argument of an operator.
  This change remains to be propagated to IA32 and PPC.


git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2399 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e

1 files changed, 8 insertions, 0 deletions

diff --git a/arm/Asmgen.v b/arm/Asmgen.v
index 3707b7f..b6cb2b3 100644
--- a/arm/Asmgen.v
+++ b/arm/Asmgen.v
@@ -267,6 +267,14 @@ Definition transl_op
   | Oaddrstack n, nil =>
       do r <- ireg_of res;
       OK (addimm r IR13 n k)
+  | Ocast8signed, a1 :: nil =>
+      do r <- ireg_of res; do r1 <- ireg_of a1;
+      OK (Pmov r (SOlslimm r1 (Int.repr 24)) ::
+          Pmov r (SOasrimm r (Int.repr 24)) :: k)
+  | Ocast16signed, a1 :: nil =>
+      do r <- ireg_of res; do r1 <- ireg_of a1;
+      OK (Pmov r (SOlslimm r1 (Int.repr 16)) ::
+          Pmov r (SOasrimm r (Int.repr 16)) :: k)
   | Oadd, a1 :: a2 :: nil =>
       do r <- ireg_of res; do r1 <- ireg_of a1; do r2 <- ireg_of a2;
       OK (Padd r r1 (SOreg r2) :: k)