1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
|
/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <cstring>
#include "core/mem_map.h"
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/armemu.h"
/***************************************************************************\
* Returns a new instantiation of the ARMulator's state *
\***************************************************************************/
ARMul_State* ARMul_NewState(ARMul_State* state)
{
memset(state, 0, sizeof(ARMul_State));
state->Emulate = RUN;
for (unsigned int i = 0; i < 16; i++) {
state->Reg[i] = 0;
for (unsigned int j = 0; j < 7; j++)
state->RegBank[j][i] = 0;
}
for (unsigned int i = 0; i < 7; i++)
state->Spsr[i] = 0;
state->Mode = USER32MODE;
state->VectorCatch = 0;
state->Aborted = false;
state->Reseted = false;
state->Inted = 3;
state->LastInted = 3;
state->lateabtSig = HIGH;
state->bigendSig = LOW;
return state;
}
/***************************************************************************\
* Call this routine to set ARMulator to model a certain processor *
\***************************************************************************/
void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
{
state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
state->is_v5 = (properties & ARM_v5_Prop) != 0;
state->is_v5e = (properties & ARM_v5e_Prop) != 0;
state->is_v6 = (properties & ARM_v6_Prop) != 0;
state->is_v7 = (properties & ARM_v7_Prop) != 0;
// Only initialse the coprocessor support once we
// know what kind of chip we are dealing with.
ARMul_CoProInit(state);
}
// Resets certain MPCore CP15 values to their ARM-defined reset values.
static void ResetMPCoreCP15Registers(ARMul_State* cpu)
{
// c0
cpu->CP15[CP15_MAIN_ID] = 0x410FB024;
cpu->CP15[CP15_TLB_TYPE] = 0x00000800;
cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;
cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;
cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;
cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;
cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;
cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;
cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;
cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011;
cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111;
cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011;
cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131;
cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141;
// c1
cpu->CP15[CP15_CONTROL] = 0x00054078;
cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;
cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;
// c2
cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;
cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;
cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;
// c3
cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;
// c7
cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000;
// c9
cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;
// c10
cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000;
cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;
cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;
// c13
cpu->CP15[CP15_PID] = 0x00000000;
cpu->CP15[CP15_CONTEXT_ID] = 0x00000000;
cpu->CP15[CP15_THREAD_UPRW] = 0x00000000;
cpu->CP15[CP15_THREAD_URO] = 0x00000000;
cpu->CP15[CP15_THREAD_PRW] = 0x00000000;
// c15
cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;
cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
}
/***************************************************************************\
* Call this routine to set up the initial machine state (or perform a RESET *
\***************************************************************************/
void ARMul_Reset(ARMul_State* state)
{
state->NextInstr = 0;
state->Reg[15] = 0;
state->Cpsr = INTBITS | SVC32MODE;
state->Mode = SVC32MODE;
state->Bank = SVCBANK;
FLUSHPIPE;
// Reset CP15
ResetMPCoreCP15Registers(state);
// This is separate from the CP15 register reset function, as
// this isn't an ARM-defined reset value; it's set by the 3DS.
//
// TODO: Whenever TLS is implemented, this should contain
// the address of the 0x200-byte TLS
state->CP15[CP15_THREAD_URO] = Memory::KERNEL_MEMORY_VADDR;
state->EndCondition = 0;
state->ErrorCode = 0;
state->NresetSig = HIGH;
state->NfiqSig = HIGH;
state->NirqSig = HIGH;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
state->abortSig = LOW;
state->AbortAddr = 1;
state->NumInstrs = 0;
}
|
