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Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp107
1 files changed, 39 insertions, 68 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 4e569fd9..c91943f2 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -34,10 +34,6 @@ enum {
THUMB = (1 << 7)
};
-#undef BITS
-#undef BIT
-#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
-#define BIT(s, n) ((s >> (n)) & 1)
#define RM BITS(sht_oper, 0, 3)
#define RS BITS(sht_oper, 8, 11)
@@ -48,10 +44,6 @@ enum {
#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32)
#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32)
-#define rotr(x,n) ( (x >> n) | ((x & ((1 << (n + 1)) - 1)) << (32 - n)) )
-
-extern void switch_mode(arm_core_t *core, uint32_t mode);
-
typedef arm_core_t arm_processor;
typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper);
@@ -231,45 +223,6 @@ unsigned int DPO(RotateRightByRegister)(arm_processor *cpu, unsigned int sht_ope
return shifter_operand;
}
-typedef struct _MiscImmeData {
- unsigned int U;
- unsigned int Rn;
- unsigned int offset_8;
-} MiscLSData;
-
-typedef struct _MiscRegData {
- unsigned int U;
- unsigned int Rn;
- unsigned int Rm;
-} MiscRegData;
-
-typedef struct _MiscImmePreIdx {
- unsigned int offset_8;
- unsigned int U;
- unsigned int Rn;
-} MiscImmePreIdx;
-
-typedef struct _MiscRegPreIdx {
- unsigned int U;
- unsigned int Rn;
- unsigned int Rm;
-} MiscRegPreIdx;
-
-typedef struct _MiscImmePstIdx {
- unsigned int offset_8;
- unsigned int U;
- unsigned int Rn;
-} MIscImmePstIdx;
-
-typedef struct _MiscRegPstIdx {
- unsigned int Rn;
- unsigned int Rm;
- unsigned int U;
-} MiscRegPstIdx;
-
-typedef struct _LSWordorUnsignedByte {
-} LDnST;
-
typedef void (*get_addr_fp_t)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw);
typedef struct _ldst_inst {
@@ -279,8 +232,9 @@ typedef struct _ldst_inst {
#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0)
int CondPassed(arm_processor *cpu, unsigned int cond);
-#define LnSWoUB(s) glue(LnSWoUB, s)
-#define MLnS(s) glue(MLnS, s)
+
+#define LnSWoUB(s) glue(LnSWoUB, s)
+#define MLnS(s) glue(MLnS, s)
#define LdnStM(s) glue(LdnStM, s)
#define W_BIT BIT(inst, 21)
@@ -3557,7 +3511,6 @@ static tdstate decode_thumb_instr(arm_processor *cpu, uint32_t inst, addr_t addr
case 26:
case 27:
if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){
- u32 cond = (tinstr & 0x0F00) >> 8;
inst_index = table_length - 4;
*ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
} else {
@@ -3697,6 +3650,9 @@ static bool InAPrivilegedMode(arm_core_t *core) {
}
unsigned InterpreterMainLoop(ARMul_State* state) {
+ #undef RM
+ #undef RS
+
#define CRn inst_cream->crn
#define OPCODE_2 inst_cream->opcode_2
#define CRm inst_cream->crm
@@ -4769,20 +4725,20 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_cream->cp_num == 15) {
if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
CP15_REG(CP15_MAIN_ID) = RD;
+ } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
+ CP15_REG(CP15_CONTROL) = RD;
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD;
- } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
- CP15_REG(CP15_CONTROL) = RD;
- } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
- CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD;
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD;
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD;
+ } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
+ CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
} else if(CRn == MMU_CACHE_OPS){
//LOG_WARNING(Core_ARM11, "cache operations have not implemented.");
} else if(CRn == MMU_TLB_OPS){
@@ -4837,12 +4793,18 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
break;
}
} else if(CRn == MMU_PID) {
- if(OPCODE_2 == 0)
+ if(OPCODE_2 == 0) {
CP15_REG(CP15_PID) = RD;
- else if(OPCODE_2 == 1)
+ } else if(OPCODE_2 == 1) {
CP15_REG(CP15_CONTEXT_ID) = RD;
- else if(OPCODE_2 == 3) {
- CP15_REG(CP15_THREAD_URO) = RD;
+ } else if (OPCODE_2 == 2) {
+ CP15_REG(CP15_THREAD_UPRW) = RD;
+ } else if(OPCODE_2 == 3) {
+ if (InAPrivilegedMode(cpu))
+ CP15_REG(CP15_THREAD_URO) = RD;
+ } else if (OPCODE_2 == 4) {
+ if (InAPrivilegedMode(cpu))
+ CP15_REG(CP15_THREAD_PRW) = RD;
} else {
LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn);
}
@@ -4930,31 +4892,40 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_cream->cp_num == 15) {
if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
RD = cpu->CP15[CP15(CP15_MAIN_ID)];
+ } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
+ RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_CONTROL)];
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
- } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
- RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
+ } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
+ RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
+ } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
+ RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
+ } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
+ RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
} else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) {
RD = cpu->CP15[CP15(CP15_FAULT_STATUS)];
- } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
- RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
- } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
- RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
} else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) {
RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
+ } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
+ RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
} else if (CRn == 13) {
- if(OPCODE_2 == 0)
+ if(OPCODE_2 == 0) {
RD = CP15_REG(CP15_PID);
- else if(OPCODE_2 == 1)
+ } else if(OPCODE_2 == 1) {
RD = CP15_REG(CP15_CONTEXT_ID);
- else if(OPCODE_2 == 3) {
+ } else if (OPCODE_2 == 2) {
+ RD = CP15_REG(CP15_THREAD_UPRW);
+ } else if(OPCODE_2 == 3) {
RD = Memory::KERNEL_MEMORY_VADDR;
+ } else if (OPCODE_2 == 4) {
+ if (InAPrivilegedMode(cpu))
+ RD = CP15_REG(CP15_THREAD_PRW);
} else {
LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn);
}
@@ -5003,7 +4974,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
}
uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
| (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
- uint32_t mask;
+ uint32_t mask = 0;
if (!inst_cream->R) {
if (InAPrivilegedMode(cpu)) {
if ((operand & StateMask) != 0) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-13 01:19:10 +0000