diff options
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 426 |
1 files changed, 255 insertions, 171 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 7ba82503..5f09d858 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -622,9 +622,7 @@ void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int } unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); unsigned int start_addr = rn - count * 4 + 4; - unsigned int end_addr = rn; - virt_addr = end_addr; virt_addr = start_addr; if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) { @@ -930,6 +928,8 @@ typedef struct _smlad_inst { unsigned int Rd; unsigned int Ra; unsigned int Rn; + unsigned int op1; + unsigned int op2; } smlad_inst; typedef struct _smla_inst { @@ -1102,10 +1102,10 @@ typedef struct _blx_1_thumb { }blx_1_thumb; typedef struct _pkh_inst { - u32 Rm; - u32 Rn; - u32 Rd; - u8 imm; + unsigned int Rm; + unsigned int Rn; + unsigned int Rd; + unsigned char imm; } pkh_inst; typedef arm_inst * ARM_INST_PTR; @@ -1738,40 +1738,31 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) return inst_base; } - ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = (BITS(inst, 12, 15) == 15) ? INDIRECT_BRANCH : NON_BRANCH; // Branch if dest is R15 - inst_cream->inst = inst; - //inst_cream->get_addr = get_calc_addr_op(inst); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); - if (BITS(inst, 12, 15) == 15) { - inst_base->br = INDIRECT_BRANCH; - } return inst_base; } ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; - - inst_cream->inst = inst; - inst_cream->get_addr = get_calc_addr_op(inst); - - if (BITS(inst, 12, 15) == 15) { - inst_base->br = INDIRECT_BRANCH; - } - return inst_base; + return INTERPRETER_TRANSLATE(ldrex)(inst, index); +} +ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ldrex)(inst, index); +} +ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(ldrex)(inst, index); } ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) { @@ -2313,25 +2304,40 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index){ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); - smlad_inst *inst_cream = (smlad_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; +ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->m = BIT(inst, 4); - inst_cream->Rn = BITS(inst, 0, 3); - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->m = BIT(inst, 5); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); - if (CHECK_RM ) - inst_base->load_r15 = 1; return inst_base; } +ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlad)(inst, index); +} +ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlad)(inst, index); +} +ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(smlad)(inst, index); +} + ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); @@ -2355,12 +2361,10 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALD"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLAW"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLSD"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLSLD"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMLA"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMLS"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMUL"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMUAD"); } ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst)); @@ -2423,7 +2427,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMUSD"); } ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); } ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) { @@ -2609,37 +2612,30 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ } ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; - inst_cream->inst = inst; - inst_cream->get_addr = get_calc_addr_op(inst); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); - if (BITS(inst, 12, 15) == 15) { - inst_base->br = INDIRECT_BRANCH; - } return inst_base; } ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; - - inst_cream->inst = inst; - inst_cream->get_addr = get_calc_addr_op(inst); - - if (BITS(inst, 12, 15) == 15) { - inst_base->br = INDIRECT_BRANCH; - } - return inst_base; + return INTERPRETER_TRANSLATE(strex)(inst, index); +} +ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(strex)(inst, index); +} +ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) +{ + return INTERPRETER_TRANSLATE(strex)(inst, index); } ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) { @@ -3341,6 +3337,11 @@ const transop_fp_t arm_instruction_trans[] = { INTERPRETER_TRANSLATE(ldc), INTERPRETER_TRANSLATE(swi), INTERPRETER_TRANSLATE(bbl), + INTERPRETER_TRANSLATE(ldrexd), + INTERPRETER_TRANSLATE(strexd), + INTERPRETER_TRANSLATE(ldrexh), + INTERPRETER_TRANSLATE(strexh), + // All the thumb instructions should be placed the end of table INTERPRETER_TRANSLATE(b_2_thumb), INTERPRETER_TRANSLATE(b_cond_thumb), @@ -3429,8 +3430,6 @@ static tdstate decode_thumb_instr(arm_processor *cpu, uint32_t inst, addr_t addr return ret; } -unsigned int *InstLength; - enum { KEEP_GOING, FETCH_EXCEPTION @@ -3515,28 +3514,6 @@ translated: #define LOG_IN_CLR skyeye_printf_in_color -int cmp(const void *x, const void *y) { - return *(unsigned long long int*)x - *(unsigned long long int *)y; -} - -void InterpreterInitInstLength(unsigned long long int *ptr, size_t size) { - int array_size = size / sizeof(void *); - unsigned long long int *InstLabel = new unsigned long long int[array_size]; - memcpy(InstLabel, ptr, size); - qsort(InstLabel, array_size, sizeof(void *), cmp); - InstLength = new unsigned int[array_size - 4]; - for (int i = 0; i < array_size - 4; i++) { - for (int j = 0; j < array_size; j++) { - if (ptr[i] == InstLabel[j]) { - InstLength[i] = InstLabel[j + 1] - InstLabel[j]; - break; - } - } - } - for (int i = 0; i < array_size - 4; i++) - LOG_DEBUG(Core_ARM11, "[%d]:%d", i, InstLength[i]); -} - int clz(unsigned int x) { int n; if (x == 0) return (32); @@ -3561,6 +3538,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { #define CRm inst_cream->crm #define CP15_REG(n) cpu->CP15[CP15(n)] #define RD cpu->Reg[inst_cream->Rd] + #define RD2 cpu->Reg[inst_cream->Rd + 1] #define RN cpu->Reg[inst_cream->Rn] #define RM cpu->Reg[inst_cream->Rm] #define RS cpu->Reg[inst_cream->Rs] @@ -3772,14 +3750,18 @@ unsigned InterpreterMainLoop(ARMul_State* state) { case 182: goto LDC_INST; \ case 183: goto SWI_INST; \ case 184: goto BBL_INST; \ - case 185: goto B_2_THUMB ; \ - case 186: goto B_COND_THUMB ; \ - case 187: goto BL_1_THUMB ; \ - case 188: goto BL_2_THUMB ; \ - case 189: goto BLX_1_THUMB ; \ - case 190: goto DISPATCH; \ - case 191: goto INIT_INST_LENGTH; \ - case 192: goto END; \ + case 185: goto LDREXD_INST; \ + case 186: goto STREXD_INST; \ + case 187: goto LDREXH_INST; \ + case 188: goto STREXH_INST; \ + case 189: goto B_2_THUMB ; \ + case 190: goto B_COND_THUMB ; \ + case 191: goto BL_1_THUMB ; \ + case 192: goto BL_2_THUMB ; \ + case 193: goto BLX_1_THUMB ; \ + case 194: goto DISPATCH; \ + case 195: goto INIT_INST_LENGTH; \ + case 196: goto END; \ } #endif @@ -3840,8 +3822,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST, - &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&B_2_THUMB, &&B_COND_THUMB, - &&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,&&INIT_INST_LENGTH,&&END + &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST, + &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, + &&INIT_INST_LENGTH,&&END }; #endif arm_inst * inst_base; @@ -4442,45 +4425,84 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LDREX_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; + unsigned int read_addr = RN; - unsigned int value = Memory::Read32(addr); - - add_exclusive_addr(cpu, addr); + add_exclusive_addr(cpu, read_addr); cpu->exclusive_state = 1; - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - if (BITS(inst_cream->inst, 12, 15) == 15) { - INC_PC(sizeof(ldst_inst)); + RD = Memory::Read32(read_addr); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); goto DISPATCH; } } cpu->Reg[15] += GET_INST_SIZE(cpu); - INC_PC(sizeof(ldst_inst)); + INC_PC(sizeof(generic_arm_inst)); FETCH_INST; GOTO_NEXT_INST; } LDREXB_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; + unsigned int read_addr = RN; - unsigned int value = Memory::Read8(addr); + add_exclusive_addr(cpu, read_addr); + cpu->exclusive_state = 1; - add_exclusive_addr(cpu, addr); + RD = Memory::Read8(read_addr); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDREXH_INST: + { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + unsigned int read_addr = RN; + + add_exclusive_addr(cpu, read_addr); cpu->exclusive_state = 1; - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - if (BITS(inst_cream->inst, 12, 15) == 15) { - INC_PC(sizeof(ldst_inst)); + RD = Memory::Read16(read_addr); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); goto DISPATCH; } } cpu->Reg[15] += GET_INST_SIZE(cpu); - INC_PC(sizeof(ldst_inst)); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + LDREXD_INST: + { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + unsigned int read_addr = RN; + + add_exclusive_addr(cpu, read_addr); + cpu->exclusive_state = 1; + // TODO(bunnei): Do we need to also make [read_addr + 4] exclusive? + + RD = Memory::Read32(read_addr); + RD2 = Memory::Read32(read_addr + 4); + + if (inst_cream->Rd == 15) { + INC_PC(sizeof(generic_arm_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); FETCH_INST; GOTO_NEXT_INST; } @@ -5382,44 +5404,59 @@ unsigned InterpreterMainLoop(ARMul_State* state) { FETCH_INST; GOTO_NEXT_INST; } + SMLAD_INST: + SMLSD_INST: + SMUAD_INST: + SMUSD_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - smlad_inst *inst_cream = (smlad_inst *)inst_base->component; - long long int rm = cpu->Reg[inst_cream->Rm]; - long long int rn = cpu->Reg[inst_cream->Rn]; - long long int ra = cpu->Reg[inst_cream->Ra]; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + const u8 op2 = inst_cream->op2; - // See SMUAD - if(inst_cream->Ra == 15) - CITRA_IGNORE_EXIT(-1); - int operand2 = (inst_cream->m)? ROTATE_RIGHT_32(rm, 16):rm; - int half_rn, half_operand2; + u32 rm_val = cpu->Reg[inst_cream->Rm]; + const u32 rn_val = cpu->Reg[inst_cream->Rn]; - half_rn = rn & 0xFFFF; - half_rn = (half_rn & 0x8000)? (0xFFFF0000|half_rn) : half_rn; + if (inst_cream->m) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); - half_operand2 = operand2 & 0xFFFF; - half_operand2 = (half_operand2 & 0x8000)? (0xFFFF0000|half_operand2) : half_operand2; + const s16 rm_lo = (rm_val & 0xFFFF); + const s16 rm_hi = ((rm_val >> 16) & 0xFFFF); + const s16 rn_lo = (rn_val & 0xFFFF); + const s16 rn_hi = ((rn_val >> 16) & 0xFFFF); - long long int product1 = half_rn * half_operand2; + const u32 product1 = (rn_lo * rm_lo); + const u32 product2 = (rn_hi * rm_hi); - half_rn = (rn & 0xFFFF0000) >> 16; - half_rn = (half_rn & 0x8000)? (0xFFFF0000|half_rn) : half_rn; + // SMUAD and SMLAD + if (BIT(op2, 1) == 0) { + RD = (product1 + product2); - half_operand2 = (operand2 & 0xFFFF0000) >> 16; - half_operand2 = (half_operand2 & 0x8000)? (0xFFFF0000|half_operand2) : half_operand2; + if (inst_cream->Ra != 15) { + RD += cpu->Reg[inst_cream->Ra]; - long long int product2 = half_rn * half_operand2; + if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) + cpu->Cpsr |= (1 << 27); + } + + if (ARMul_AddOverflowQ(product1, product2)) + cpu->Cpsr |= (1 << 27); + } + // SMUSD and SMLSD + else { + RD = (product1 - product2); - long long int signed_ra = (ra & 0x80000000)? (0xFFFFFFFF00000000LL) | ra : ra; - long long int result = product1 + product2 + signed_ra; - cpu->Reg[inst_cream->Rd] = result & 0xFFFFFFFF; + if (inst_cream->Ra != 15) { + RD += cpu->Reg[inst_cream->Ra]; - // TODO: FIXME should check Signed overflow + if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) + cpu->Cpsr |= (1 << 27); + } + } } + cpu->Reg[15] += GET_INST_SIZE(cpu); - INC_PC(sizeof(umlal_inst)); + INC_PC(sizeof(smlad_inst)); FETCH_INST; GOTO_NEXT_INST; } @@ -5452,15 +5489,15 @@ unsigned InterpreterMainLoop(ARMul_State* state) { FETCH_INST; GOTO_NEXT_INST; } + SMLALXY_INST: SMLALD_INST: SMLAW_INST: - SMLSD_INST: SMLSLD_INST: SMMLA_INST: SMMLS_INST: SMMUL_INST: - SMUAD_INST: + SMUL_INST: { if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { @@ -5528,8 +5565,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { GOTO_NEXT_INST; } - SMUSD_INST: SRS_INST: + SSAT_INST: { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { @@ -5757,46 +5794,96 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STREX_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; - unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)]; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; - int dest_reg = BITS(inst_cream->inst, 12, 15); - if((exclusive_detect(cpu, addr) == 0) && (cpu->exclusive_state == 1)){ - remove_exclusive(cpu, addr); - cpu->Reg[dest_reg] = 0; + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); cpu->exclusive_state = 0; - Memory::Write32(addr, value); + Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]); + RD = 0; } else { // Failed to write due to mutex access - cpu->Reg[dest_reg] = 1; + RD = 1; } } cpu->Reg[15] += GET_INST_SIZE(cpu); - INC_PC(sizeof(ldst_inst)); + INC_PC(sizeof(generic_arm_inst)); FETCH_INST; GOTO_NEXT_INST; } STREXB_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; - unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)] & 0xff; - int dest_reg = BITS(inst_cream->inst, 12, 15); - if((exclusive_detect(cpu, addr) == 0) && (cpu->exclusive_state == 1)){ - remove_exclusive(cpu, addr); - cpu->Reg[dest_reg] = 0; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); cpu->exclusive_state = 0; - Memory::Write8(addr, value); + + Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]); + RD = 0; } else { - cpu->Reg[dest_reg] = 1; + // Failed to write due to mutex access + RD = 1; } } cpu->Reg[15] += GET_INST_SIZE(cpu); - INC_PC(sizeof(ldst_inst)); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STREXD_INST: + { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); + cpu->exclusive_state = 0; + // TODO(bunnei): Remove exclusive from [write_addr + 4] if we implement this in LDREXD + + Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]); + Memory::Write32(write_addr + 4, cpu->Reg[inst_cream->Rm + 1]); + RD = 0; + } + else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } + STREXH_INST: + { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + + if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { + remove_exclusive(cpu, write_addr); + cpu->exclusive_state = 0; + + Memory::Write16(write_addr, cpu->Reg[inst_cream->Rm]); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(generic_arm_inst)); FETCH_INST; GOTO_NEXT_INST; } @@ -6564,9 +6651,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } INIT_INST_LENGTH: { -#if defined __GNUC__ || defined __clang__ - InterpreterInitInstLength((unsigned long long int *)InstLabel, sizeof(InstLabel)); -#endif cpu->NumInstrsToExecute = 0; return num_instrs; } |