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authorGravatar Normmatt <normmatt234@gmail.com>2014-12-17 02:28:12 -0500
committerGravatar Lioncash <mathew1800@gmail.com>2014-12-17 03:16:40 -0500
commitefebd5589a53f3f21f36d1a3c92a4e567bd89c8e (patch)
tree74de1f4484345d3897f41828353c5c5eadd1b3a4 /src
parentfdb4ef5210ab064a71fbdad13aa9cf897f6d94e4 (diff)
armemu: Fix SXTAH
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/interpreter/armemu.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 5752d116..84332329 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -6057,7 +6057,8 @@ L_stm_s_takeabort:
return 1;
}
- case 0x6b: {
+ case 0x6b:
+ {
ARMword Rm;
int ror = -1;
@@ -6088,7 +6089,7 @@ L_stm_s_takeabort:
if (ror == -1)
break;
- Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF);
+ Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF;
if (Rm & 0x8000)
Rm |= 0xffff0000;