diff options
| author |  bunnei <ericbunnie@gmail.com> | 2014-04-04 22:24:41 -0400 |
|---|---|---|
| committer | bunnei <ericbunnie@gmail.com> | 2014-04-04 22:24:41 -0400 |
| commit | f5f6428b97dc2508f252c3419d26d263947539c7 (patch) | |
| tree | 6fa99d344794596154bf7d820aef5ae6a7edfb19 /src/core | |
| parent | 66299a48801fffe8e7920fc87b2d3806a4816dce (diff) | |
got rid of some really poorly named macros in SkyEye core
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/src/arm/interpreter/armemu.cpp | 4 | ||||
| -rw-r--r-- | src/core/src/arm/interpreter/armemu.h | 11 | ||||
| -rw-r--r-- | src/core/src/arm/interpreter/armsupp.cpp | 3 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/core/src/arm/interpreter/armemu.cpp b/src/core/src/arm/interpreter/armemu.cpp index 5e3a9cfb..46c51fbe 100644 --- a/src/core/src/arm/interpreter/armemu.cpp +++ b/src/core/src/arm/interpreter/armemu.cpp @@ -5826,7 +5826,7 @@ LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) if (BIT (15) && !state->Aborted) /* PC is in the reg list. */ - WriteR15Branch (state, PC); + WriteR15Branch(state, (state->Reg[15] & PCMASK)); /* To write back the final register. */ /* ARMul_Icycles (state, 1, 0L);*/ @@ -5959,7 +5959,7 @@ LoadSMult (ARMul_State * state, ARMul_CPSRAltered (state); } - WriteR15 (state, PC); + WriteR15 (state, (state->Reg[15] & PCMASK)); #else //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode == USER26MODE || state->Mode == USER32MODE ) { diff --git a/src/core/src/arm/interpreter/armemu.h b/src/core/src/arm/interpreter/armemu.h index d4afa8e2..2ab317fd 100644 --- a/src/core/src/arm/interpreter/armemu.h +++ b/src/core/src/arm/interpreter/armemu.h @@ -166,7 +166,6 @@ extern ARMword isize; #define PCWRAP(pc) ((pc) & R15PCBITS) #endif -#define PC (state->Reg[15] & PCMASK) #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) #define R15INT (state->Reg[15] & R15INTBITS) #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) @@ -181,11 +180,11 @@ extern ARMword isize; #define ER15INT (IFFLAGS << 26) #define EMODE (state->Mode) -#ifdef MODET -#define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) -#else -#define CPSR (ECC | EINT | EMODE) -#endif +//#ifdef MODET +//#define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) +//#else +//#define CPSR (ECC | EINT | EMODE) +//#endif #ifdef MODE32 #define PATCHR15 diff --git a/src/core/src/arm/interpreter/armsupp.cpp b/src/core/src/arm/interpreter/armsupp.cpp index 75d326f2..a0c866c1 100644 --- a/src/core/src/arm/interpreter/armsupp.cpp +++ b/src/core/src/arm/interpreter/armsupp.cpp @@ -123,7 +123,8 @@ ARMul_GetCPSR (ARMul_State * state) { //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator //return (CPSR | state->Cpsr); for gdb20030716 - return (CPSR); //had be tested in old skyeye with gdb5.0-5.3 + // NOTE(bunnei): Changed this from [now] commented out macro "CPSR" + return ((ECC | EINT | EMODE | (TFLAG << 5))); //had be tested in old skyeye with gdb5.0-5.3 } /* This routine sets the value of the CPSR. */ |