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authorGravatar bunnei <bunneidev@gmail.com>2015-03-17 19:13:06 -0400
committerGravatar bunnei <bunneidev@gmail.com>2015-03-17 19:13:06 -0400
commit580b3178216656e31a505a5cd5d743befabfcde5 (patch)
tree92707c5b40cd1dab695d7920ba381abb61dadd23 /src/core/hw
parent0bb4b77b784dfb1e405c71033bfa9988ac024a2d (diff)
parent23b401c3ac6ac1ab9e9cf9ffa9d9a03daa20dfb7 (diff)
Merge pull request #650 from Subv/scaling
GPU: Fixed the bit 25 in the display transfer flags.
Diffstat (limited to 'src/core/hw')
-rw-r--r--src/core/hw/gpu.cpp12
-rw-r--r--src/core/hw/gpu.h9
2 files changed, 16 insertions, 5 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index 07443616..e6983a22 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -118,8 +118,14 @@ inline void Write(u32 addr, const T data) {
u8* src_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalInputAddress()));
u8* dst_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalOutputAddress()));
- unsigned horizontal_scale = (config.scale_horizontally != 0) ? 2 : 1;
- unsigned vertical_scale = (config.scale_vertically != 0) ? 2 : 1;
+ if (config.scaling > config.ScaleXY) {
+ LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u", config.scaling.Value());
+ UNIMPLEMENTED();
+ break;
+ }
+
+ unsigned horizontal_scale = (config.scaling != config.NoScale) ? 2 : 1;
+ unsigned vertical_scale = (config.scaling == config.ScaleXY) ? 2 : 1;
u32 output_width = config.output_width / horizontal_scale;
u32 output_height = config.output_height / vertical_scale;
@@ -140,7 +146,7 @@ inline void Write(u32 addr, const T data) {
break;
}
- // TODO(Subv): Blend the pixels when horizontal / vertical scaling is enabled,
+ // TODO(Subv): Implement the box filter when scaling is enabled
// right now we're just skipping the extra pixels.
for (u32 y = 0; y < output_height; ++y) {
for (u32 x = 0; x < output_width; ++x) {
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index e8552d85..c8f88449 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -188,6 +188,12 @@ struct Regs {
BitField<16, 16, u32> input_height;
};
+ enum ScalingMode : u32 {
+ NoScale = 0, // Doesn't scale the image
+ ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
+ ScaleXY = 2, // Downscales the image in half in both the X and Y axes and applies a box filter
+ };
+
union {
u32 flags;
@@ -197,8 +203,7 @@ struct Regs {
BitField< 8, 3, PixelFormat> input_format;
BitField<12, 3, PixelFormat> output_format;
- BitField<24, 1, u32> scale_horizontally;
- BitField<25, 1, u32> scale_vertically;
+ BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
};
INSERT_PADDING_WORDS(0x1);