diff options
author | Lioncash <mathew1800@gmail.com> | 2015-03-26 15:25:04 -0400 |
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committer | Lioncash <mathew1800@gmail.com> | 2015-04-02 00:20:52 -0400 |
commit | 490df716f327b1cff6097f607c13f08f948dbf3b (patch) | |
tree | 0ba1f8b3b58ac4c31722b5fac1dad33f0adef2ca /src/core/arm/skyeye_common/arm_regformat.h | |
parent | 5e5954c63b1a22ba2d333d23ae4c194798fe5412 (diff) |
dyncom: Move CP15 register writing into its own function.
Also implements writing to the rest of the ARM11 MPCore CP15 register set.
Diffstat (limited to 'src/core/arm/skyeye_common/arm_regformat.h')
-rw-r--r-- | src/core/arm/skyeye_common/arm_regformat.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h index fb5b70f1..c232376e 100644 --- a/src/core/arm/skyeye_common/arm_regformat.h +++ b/src/core/arm/skyeye_common/arm_regformat.h @@ -105,7 +105,40 @@ enum { CP15_IFAR, // c7 - Cache operation registers + CP15_WAIT_FOR_INTERRUPT, CP15_PHYS_ADDRESS, + CP15_INVALIDATE_INSTR_CACHE, + CP15_INVALIDATE_INSTR_CACHE_USING_MVA, + CP15_INVALIDATE_INSTR_CACHE_USING_INDEX, + CP15_FLUSH_PREFETCH_BUFFER, + CP15_FLUSH_BRANCH_TARGET_CACHE, + CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY, + CP15_INVALIDATE_DATA_CACHE, + CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA, + CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX, + CP15_INVALIDATE_DATA_AND_INSTR_CACHE, + CP15_CLEAN_DATA_CACHE, + CP15_CLEAN_DATA_CACHE_LINE_USING_MVA, + CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX, + CP15_DATA_SYNC_BARRIER, + CP15_DATA_MEMORY_BARRIER, + CP15_CLEAN_AND_INVALIDATE_DATA_CACHE, + CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA, + CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX, + + // c8 - TLB operations + CP15_INVALIDATE_ITLB, + CP15_INVALIDATE_ITLB_SINGLE_ENTRY, + CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH, + CP15_INVALIDATE_ITLB_ENTRY_ON_MVA, + CP15_INVALIDATE_DTLB, + CP15_INVALIDATE_DTLB_SINGLE_ENTRY, + CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH, + CP15_INVALIDATE_DTLB_ENTRY_ON_MVA, + CP15_INVALIDATE_UTLB, + CP15_INVALIDATE_UTLB_SINGLE_ENTRY, + CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH, + CP15_INVALIDATE_UTLB_ENTRY_ON_MVA, // c9 - Data cache lockdown register CP15_DATA_CACHE_LOCKDOWN, |