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authorGravatar Lioncash <mathew1800@gmail.com>2014-12-17 15:34:58 -0500
committerGravatar Lioncash <mathew1800@gmail.com>2014-12-17 15:40:10 -0500
commit58dc5547333cfb946f3881eb746811794a0f39a7 (patch)
treee47a81d31aa2ef319e1a7d2f1f23f191b8ad548c /src/core/arm/interpreter
parente6f440ea7f4d5f8c075a5735747ef8facbb4699a (diff)
armemu: Fix SSUB16
Broken from the same reason SADD16 was. The lo part of the result should only be constructed from the lo halfwords of rm and rn. The hi part of the result should only be constructed from the hi halfwords of rm and rn.
Diffstat (limited to 'src/core/arm/interpreter')
-rw-r--r--src/core/arm/interpreter/armemu.cpp16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 1a589e39..2b5d8c68 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -5801,14 +5801,14 @@ L_stm_s_takeabort:
break;
case 0x61:
if ((instr & 0xFF0) == 0xf70) { //ssub16
- u8 tar = BITS(12, 15);
- u8 src1 = BITS(16, 19);
- u8 src2 = BITS(0, 3);
- s16 a1 = (state->Reg[src1] & 0xFFFF);
- s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
- s16 b1 = (state->Reg[src2] & 0xFFFF);
- s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
- state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10);
+ const u8 rd_idx = BITS(12, 15);
+ const u8 rm_idx = BITS(0, 3);
+ const u8 rn_idx = BITS(16, 19);
+ const s16 rn_lo = (state->Reg[rn_idx] & 0xFFFF);
+ const s16 rn_hi = ((state->Reg[rn_idx] >> 16) & 0xFFFF);
+ const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
+ const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
+ state->Reg[rd_idx] = ((rn_lo - rm_lo) & 0xFFFF) | (((rn_hi - rm_hi) & 0xFFFF) << 16);
return 1;
} else if ((instr & 0xFF0) == 0xf10) { //sadd16
const u8 rd_idx = BITS(12, 15);