diff options
author | Lioncash <mathew1800@gmail.com> | 2015-04-06 09:25:11 -0400 |
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committer | Lioncash <mathew1800@gmail.com> | 2015-04-06 09:26:04 -0400 |
commit | 23dd2ca8a6757d356cbc7954a431bfc227ec6d9a (patch) | |
tree | 6411f282ef284b033ab14452bd1d6a41701fd065 /src/core/arm/interpreter/arminit.cpp | |
parent | e628ed481079d26cad4980f5094dbca16bae96c8 (diff) |
dyncom: Properly return the value of the user RO thread register
Diffstat (limited to 'src/core/arm/interpreter/arminit.cpp')
-rw-r--r-- | src/core/arm/interpreter/arminit.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 71011537..c6b8197f 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -16,6 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <cstring> +#include "core/mem_map.h" #include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armemu.h" @@ -138,8 +139,16 @@ void ARMul_Reset(ARMul_State* state) state->Bank = SVCBANK; FLUSHPIPE; + // Reset CP15 ResetMPCoreCP15Registers(state); + // This is separate from the CP15 register reset function, as + // this isn't an ARM-defined reset value; it's set by the 3DS. + // + // TODO: Whenever TLS is implemented, this should contain + // the address of the 0x200-byte TLS + state->CP15[CP15(CP15_THREAD_URO)] = Memory::KERNEL_MEMORY_VADDR; + state->EndCondition = 0; state->ErrorCode = 0; |