diff options
| author |  Lioncash <mathew1800@gmail.com> | 2015-05-13 17:29:59 -0400 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-05-14 16:24:39 -0400 |
| commit | be0119be0816c3bb431e17916659453c1d25b4d8 (patch) | |
| tree | b3bab345e2d03f7e227e1fad1aae0f4863fec39e /src/core/arm/dyncom/arm_dyncom_dec.cpp | |
| parent | e83bc5b7ee45ae24821c4cd185dd6a14dbd3b4d4 (diff) | |
dyncom: Move exclusive load/stores above bbl and swi in the decoding table
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_dec.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 12181d0e..411850f0 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -190,12 +190,12 @@ const ISEITEM arm_instruction[] = { { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 }, { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 }, { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 }, - { "swi", 1, 0, 24, 27, 0x0000000f }, - { "bbl", 1, 0, 25, 27, 0x00000005 }, { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 }, { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, + { "swi", 1, 0, 24, 27, 0x0000000f }, + { "bbl", 1, 0, 25, 27, 0x00000005 }, }; const ISEITEM arm_exclusion_code[] = { @@ -383,12 +383,12 @@ const ISEITEM arm_exclusion_code[] = { { "cdp", 0, 0, 0 }, { "stc", 0, 0, 0 }, { "ldc", 0, 0, 0 }, - { "swi", 0, 0, 0 }, - { "bbl", 0, 0, 0 }, { "ldrexd", 0, ARMV6K, 0 }, { "strexd", 0, ARMV6K, 0 }, { "ldrexh", 0, ARMV6K, 0 }, { "strexh", 0, ARMV6K, 0 }, + { "swi", 0, 0, 0 }, + { "bbl", 0, 0, 0 }, { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4] { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3] |