diff options
| author |  Lioncash <mathew1800@gmail.com> | 2015-05-14 15:41:40 -0400 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-05-14 16:25:02 -0400 |
| commit | 8cd72428c9c7314cc7add4b5619b62eab035977f (patch) | |
| tree | a9c1fc77edda58dba2ad49138c7dbb539aa86906 /src/core/arm/dyncom/arm_dyncom_dec.cpp | |
| parent | 699b67d7cfacb48c65df3a6f7e5adc55aebd4c2a (diff) | |
dyncom: Add ARMv6K NOP and hint instructions to the decoding table
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_dec.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index d0d37bea..3887189f 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -198,6 +198,11 @@ const ISEITEM arm_instruction[] = { { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, + { "nop", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000000 }, + { "yield", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000001 }, + { "wfe", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000002 }, + { "wfi", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000003 }, + { "sev", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000004 }, { "swi", 1, 0, 24, 27, 0x0000000f }, { "bbl", 1, 0, 25, 27, 0x00000005 }, }; @@ -395,6 +400,11 @@ const ISEITEM arm_exclusion_code[] = { { "strexd", 0, ARMV6K, 0 }, { "ldrexh", 0, ARMV6K, 0 }, { "strexh", 0, ARMV6K, 0 }, + { "nop", 0, ARMV6K, 0 }, + { "yield", 0, ARMV6K, 0 }, + { "wfe", 0, ARMV6K, 0 }, + { "wfi", 0, ARMV6K, 0 }, + { "sev", 0, ARMV6K, 0 }, { "swi", 0, 0, 0 }, { "bbl", 0, 0, 0 }, |