/* Copyright 2015 The TensorFlow Authors. All Rights Reserved. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. ==============================================================================*/ #if GOOGLE_CUDA #define EIGEN_USE_GPU #include #include "tensorflow/core/kernels/resize_nearest_neighbor_op.h" #include "tensorflow/core/framework/register_types.h" #include "tensorflow/core/framework/tensor_types.h" #include "tensorflow/core/platform/types.h" #include "tensorflow/core/util/cuda_kernel_helper.h" namespace tensorflow { typedef Eigen::GpuDevice GPUDevice; namespace { template __global__ void ResizeNearestNeighborNHWC( const int nthreads, const T* bottom_data, const int in_height, const int in_width, const int channels, const int out_height, const int out_width, const float height_scale, const float width_scale, T* top_data) { CUDA_1D_KERNEL_LOOP(index, nthreads) { int n = index; int c = n % channels; n /= channels; int out_x = n % out_width; n /= out_width; int out_y = n % out_height; n /= out_height; const T* bottom_data_n = bottom_data + n * channels * in_height * in_width; const int in_y = min((align_corners) ? static_cast(roundf(out_y * height_scale)) : static_cast(floorf(out_y * height_scale)), in_height - 1); const int in_x = min((align_corners) ? static_cast(roundf(out_x * width_scale)) : static_cast(floorf(out_x * width_scale)), in_width - 1); const int idx = (in_y * in_width + in_x) * channels + c; top_data[index] = ldg(bottom_data_n + idx); } } template __global__ void ResizeNearestNeighborBackwardNHWC( const int nthreads, const T* top_diff, const int in_height, const int in_width, const int channels, const int out_height, const int out_width, const float height_scale, const float width_scale, T* bottom_diff) { CUDA_1D_KERNEL_LOOP(index, nthreads) { int n = index; int c = n % channels; n /= channels; int in_x = n % in_width; n /= in_width; int in_y = n % in_height; n /= in_height; T* bottom_diff_n = bottom_diff + n * channels * out_height * out_width; const int out_y = min((align_corners) ? static_cast(roundf(in_y * height_scale)) : static_cast(floorf(in_y * height_scale)), out_height - 1); const int out_x = min((align_corners) ? static_cast(roundf(in_x * width_scale)) : static_cast(floorf(in_x * width_scale)), out_width - 1); const int idx = (out_y * out_width + out_x) * channels + c; CudaAtomicAdd(bottom_diff_n + idx, ldg(top_diff + index)); } } } // namespace namespace functor { // Partial specialization of ResizeNearestNeighbor functor for a GPUDevice. template struct ResizeNearestNeighbor { bool operator()(const GPUDevice& d, typename TTypes::ConstTensor input, const float height_scale, const float width_scale, typename TTypes::Tensor output) { const int batch_size = input.dimension(0); const int64 in_height = input.dimension(1); const int64 in_width = input.dimension(2); const int channels = input.dimension(3); const int64 out_height = output.dimension(1); const int64 out_width = output.dimension(2); const int output_size = batch_size * out_height * out_width * channels; if (output_size == 0) return true; CudaLaunchConfig config = GetCudaLaunchConfig(output_size, d); ResizeNearestNeighborNHWC <<>>( output_size, input.data(), in_height, in_width, channels, out_height, out_width, height_scale, width_scale, output.data()); return d.ok(); } }; #define DECLARE_GPU_SPEC(T) \ template struct ResizeNearestNeighbor; \ template struct ResizeNearestNeighbor; TF_CALL_GPU_NUMBER_TYPES(DECLARE_GPU_SPEC); #undef DECLARE_GPU_SPEC // Partial specialization of ResizeNearestNeighborGrad functor for a GPUDevice. template struct ResizeNearestNeighborGrad { bool operator()(const GPUDevice& d, typename TTypes::ConstTensor input, const float height_scale, const float width_scale, typename TTypes::Tensor output) { const int batch_size = input.dimension(0); const int64 in_height = input.dimension(1); const int64 in_width = input.dimension(2); const int channels = input.dimension(3); const int64 out_height = output.dimension(1); const int64 out_width = output.dimension(2); const int output_size = batch_size * channels * out_height * out_width; CudaLaunchConfig output_config = GetCudaLaunchConfig(output_size, d); SetZero<<>>(output_size, output.data()); if (!d.ok()) return false; const int input_size = batch_size * channels * in_height * in_width; if (input_size == 0) return true; CudaLaunchConfig input_config = GetCudaLaunchConfig(input_size, d); ResizeNearestNeighborBackwardNHWC <<>>(input_config.virtual_thread_count, input.data(), in_height, in_width, channels, out_height, out_width, height_scale, width_scale, output.data()); return d.ok(); } }; #define DECLARE_GPU_SPEC(T) \ template struct ResizeNearestNeighborGrad; \ template struct ResizeNearestNeighborGrad; TF_CALL_GPU_NUMBER_TYPES(DECLARE_GPU_SPEC); #undef DECLARE_GPU_SPEC } // namespace functor } // namespace tensorflow #endif // GOOGLE_CUDA