blob: 337523dc513a7f9ab1e4cfec3f8a935bc835a619 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
# vector scalar instructions
stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3
utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3
movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3
movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3
fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3
fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3
vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3
vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3
vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3
vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3
vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3
venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3
venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3
venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3
venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3
# vector load mem instructions
# 3=d
# 2=seg 2=w
# 1=st 1=seg 1=f 1=s 1=h
# 0=u 0=etc 0=x 0=u 0=b
# ----------------------------------------------------------------------------
# mem padding type seg x/f u/s width opcode
# unit stride | | | | | | | |
# xloads | | | | | | | |
vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# mem padding type seg x/f u/s width opcode
# stride | | | | | | | |
# xloads | | | | | | | |
vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# mem padding type seg x/f u/s width opcode
# segment | | | | | | | |
# xloads | | | | | | | |
vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# seg x/f u/s width opcode
# stride segment | | | | |
# xloads | | | | |
vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3
vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3
vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3
vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3
vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3
vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3
vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3
# floads
vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3
vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3
# vector store mem instructions
# mem padding type seg x/f u/s width opcode
# unit stride | | | | | | | |
# xstores | | | | | | | |
vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# mem padding type seg x/f u/s width opcode
# stride | | | | | | | |
# xstores | | | | | | | |
vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# mem padding type seg x/f u/s width opcode
# segment | | | | | | | |
# xstores | | | | | | | |
vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# seg x/f u/s width opcode
# stride segment | | | | |
# xstores | | | | |
vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3
vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3
vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3
vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3
# fstores
vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3
vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3
# other vector register instructions
vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3
vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3
vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3
vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3
vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3
vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3
vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3
vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3
vvcfg 31..27=0 rs1 rs2 16..11=0 10..8=4 7=0 6..2=0x1C 1..0=3
vtcfg 31..27=0 rs1 rs2 16..11=1 10..8=4 7=0 6..2=0x1C 1..0=3
# other vector immediate instructions
vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3
vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3
vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3
vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3
|