#!/usr/bin/python

import math
import sys
import tokenize

namelist = []
match = {}
mask = {}
arguments = {}

arglut = {}
arglut['rd'] = (31,27)
arglut['rs1'] = (26,22)
arglut['rs2'] = (21,17)
arglut['rs3'] = (16,12)
arglut['rm'] = (11,9)
arglut['imm25'] = (31,7)
arglut['imm20'] = (26,7)
arglut['imm12'] = (21,10)
arglut['imm12hi'] = (31,27)
arglut['imm12lo'] = (16,10)
arglut['shamt'] = (15,10)
arglut['shamtw'] = (14,10)

arglut['crd'] = (9,5)
arglut['crs2'] = (9,5)
arglut['crs1'] = (14,10)
arglut['crds'] = (15,13)
arglut['crs2s'] = (15,13)
arglut['crs2bs'] = (7,5)
arglut['crs1s'] = (12,10)
arglut['cimm6'] = (15,10)
arglut['cimm10'] = (14,5)
arglut['cimm5'] = (9,5)

typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,,8=r4rm,9=rrm,10=b
typelut[0x03] = 3
typelut[0x07] = 3
typelut[0x13] = 3
typelut[0x1B] = 3
typelut[0x23] = 10
typelut[0x27] = 10
typelut[0x2B] = 4
typelut[0x2F] = 4
typelut[0x33] = 4
typelut[0x37] = 2
typelut[0x17] = 2
typelut[0x3B] = 4
typelut[0x43] = 8
typelut[0x47] = 8
typelut[0x4B] = 8
typelut[0x4F] = 8
typelut[0x53] = 9
typelut[0x63] = 10
typelut[0x67] = 1
typelut[0x6B] = 3
typelut[0x6F] = 1
typelut[0x77] = 4
typelut[0x7B] = 4

# XXX RVC
for i in range(0,3):
  for j in range(0,8):
    typelut[j*4+i] = 0

# vector opcodes
typelut[0x0B] = 4
typelut[0x0F] = 4
typelut[0x73] = 4

opcode_base = 0
opcode_size = 7
funct_base = 7
funct_size = 3

def binary(n, digits=0):
  rep = bin(n)[2:]
  return rep if digits == 0 else ('0' * (digits - len(rep))) + rep

def make_disasm_table(match,mask):
  print '/* Automatically generated by parse-opcodes */'
  for name,match in match.iteritems():
    name2 = name.upper().replace('.','_')
    print '#define MATCH_%s %s' % (name2, hex(match))
    print '#define  MASK_%s %s' % (name2, hex(mask[name]))

def make_isasim(match, mask):
  for name in match.iterkeys():
    name2 = name.replace('.','_')
    print 'DECLARE_INSN(%s, 0x%x, 0x%x)' % (name2, match[name], mask[name])

def yank(num,start,len):
  return (num >> start) & ((1 << len) - 1)

def str_arg(arg0,arg1,match,arguments):
  if arg0 in arguments:
    return arg0
  elif arg1 in arguments:
    return arg1
  else:
    start = arglut[arg0][1]
    len = arglut[arg0][0] - arglut[arg0][1] + 1
    return binary(yank(match,start,len),len)

def str_inst(name,arguments):
  ret = name.upper() + ' '
  if 'imm12hi' in arguments and 'imm12lo' in arguments:
    arguments.remove('imm12hi')
    arguments.remove('imm12lo')
    arguments.append('imm12')
  for idx in range(len(arguments)):
    ret = ret + arguments[idx]
    if idx != len(arguments)-1:
      ret = ret + ','
  return ret

def print_unimp_type(name,match,arguments):
  print """
&
\\multicolumn{10}{|c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    '0'*32, \
    'UNIMP' \
  )

def print_j_type(name,match,arguments):
  print """
&
\\multicolumn{9}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('imm25','',match,arguments), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_lui_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{8}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('imm20','',match,arguments), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_b_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{4}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('imm12hi','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    str_arg('rs2','',match,arguments), \
    str_arg('imm12lo','',match,arguments), \
    binary(yank(match,funct_base,funct_size),funct_size), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_i_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{5}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    str_arg('imm12','',match,arguments), \
    binary(yank(match,funct_base,funct_size),funct_size), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_ish_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    binary(yank(match,16,6),6), \
    str_arg('shamt','',match,arguments), \
    binary(yank(match,funct_base,funct_size),funct_size), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_ishw_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    binary(yank(match,15,7),7), \
    str_arg('shamtw','',match,arguments), \
    binary(yank(match,funct_base,funct_size),funct_size), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_r_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{4}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    str_arg('rs2','',match,arguments), \
    binary(yank(match,10,7),7), \
    binary(yank(match,funct_base,funct_size),funct_size), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_r4_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    str_arg('rs2','',match,arguments), \
    str_arg('rs3','',match,arguments), \
    binary(yank(match,7,5),5), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_r_rm_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    str_arg('rs2','',match,arguments), \
    binary(yank(match,12,5),5), \
    str_arg('rm','',match,arguments), \
    binary(yank(match,7,2),2), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_r4_rm_type(name,match,arguments):
  print """
&
\\multicolumn{1}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
  """ % \
  ( \
    str_arg('rd','',match,arguments), \
    str_arg('rs1','',match,arguments), \
    str_arg('rs2','',match,arguments), \
    str_arg('rs3','',match,arguments), \
    str_arg('rm','',match,arguments), \
    binary(yank(match,7,2),2), \
    binary(yank(match,opcode_base,opcode_size),opcode_size), \
    str_inst(name,arguments) \
  )

def print_header():
  print """
\\newpage

\\begin{table}[p]
\\begin{small}
\\begin{center}
\\begin{tabular}{rccccccccccl}
                      &
\\instbitrange{31}{27} &
\\instbitrange{26}{22} &
\\instbitrange{21}{17} &
\\instbit{16} &
 &
\\instbitrange{}{12} &
\\instbitrange{11}{10} &
\\instbit{9} &
\\instbitrange{}{7} &
\\instbitrange{6}{0} \\\\
\\cline{2-11}
&
\\multicolumn{9}{|c|}{jump target} &
\\multicolumn{1}{c|}{opcode} & J-type \\\\
\\cline{2-11}
&
\\multicolumn{1}{|c|}{rd} &
\\multicolumn{8}{c|}{upper immediate} &
\\multicolumn{1}{c|}{opcode} & U-type \\\\
\\cline{2-11}
&
\\multicolumn{1}{|c|}{rd} &
\\multicolumn{1}{c|}{rs1} &
\\multicolumn{1}{c|}{imm[11:7]} &
\\multicolumn{4}{c|}{imm[6:0]} &
\\multicolumn{2}{c|}{funct3} &
\\multicolumn{1}{c|}{opcode} & I-type \\\\
\\cline{2-11}
&
\\multicolumn{1}{|c|}{imm[11:7]} &
\\multicolumn{1}{c|}{rs1} &
\\multicolumn{1}{c|}{rs2} &
\\multicolumn{4}{c|}{imm[6:0]} &
\\multicolumn{2}{c|}{funct3} &
\\multicolumn{1}{c|}{opcode} & B-type \\\\
\\cline{2-11}
&
\\multicolumn{1}{|c|}{rd} &
\\multicolumn{1}{c|}{rs1} &
\\multicolumn{1}{c|}{rs2} &
\\multicolumn{6}{c|}{funct10} &
\\multicolumn{1}{c|}{opcode} & R-type \\\\
\\cline{2-11}
&
\\multicolumn{1}{|c|}{rd} &
\\multicolumn{1}{c|}{rs1} &
\\multicolumn{1}{c|}{rs2} &
\\multicolumn{3}{c|}{rs3} &
\\multicolumn{3}{c|}{funct5} &
\\multicolumn{1}{c|}{opcode} & R4-type \\\\
\\cline{2-11}
  """

def print_subtitle(title):
  print """
&
\\multicolumn{10}{c}{} & \\\\
&
\\multicolumn{10}{c}{\\bf %s} & \\\\
\\cline{2-11}
  """ % title

def print_footer(caption):
  print """
\\end{tabular}
\\end{center}
\\end{small}
%s
\\label{instr-table}
\\end{table}
  """ % (caption and '\\caption{Instruction listing for RISC-V}' or '')

def print_inst(n):
  if 'shamt' in arguments[n]:
    print_ish_type(n, match[n], arguments[n])
  elif 'shamtw' in arguments[n]:
    print_ishw_type(n, match[n], arguments[n])
  elif 'imm25' in arguments[n]:
    print_j_type(n, match[n], arguments[n])
  elif 'imm20' in arguments[n]:
    print_lui_type(n, match[n], arguments[n])
  elif 'imm12' in arguments[n]:
    print_i_type(n, match[n], arguments[n])
  elif 'imm12hi' in arguments[n]:
    print_b_type(n, match[n], arguments[n])
  elif 'rs3' in arguments[n] and 'rm' in arguments[n]:
    print_r4_rm_type(n, match[n], arguments[n])
  elif 'rs3' in arguments[n]:
    print_r4_type(n, match[n], arguments[n])
  elif 'rm' in arguments[n] or \
      filter(lambda x: x in n, ['fmin','fmax','fsgnj','fmv','feq','flt','fle','mtfsr','mffsr']):
    print_r_rm_type(n, match[n], arguments[n])
  else:
    print_r_type(n, match[n], arguments[n])

def print_insts(*names):
  for n in names:
    print_inst(n)

def make_latex_table():
  print_header()
  print_subtitle('RV32I Instruction Subset')
  print_insts('lui', 'auipc')
  print_insts('j', 'jal', 'jalr', 'beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu')
  print_insts('lb', 'lh', 'lw', 'lbu', 'lhu', 'sb', 'sh', 'sw')
  print_insts('addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi')
  print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and')
  print_insts('fence.i', 'fence')
  print_insts('syscall', 'break', 'rdcycle', 'rdtime', 'rdinstret')
  print_footer(0)

  print_header()
  print_subtitle('RV64I Instruction Subset (in addition to RV32I)')
  print_insts('lwu', 'ld', 'sd')
  print_insts('addiw', 'slliw', 'srliw', 'sraiw')
  print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw')
  print_subtitle('RV32M Instruction Subset')
  print_insts('mul', 'mulh', 'mulhsu', 'mulhu')
  print_insts('div', 'divu', 'rem', 'remu')
  print_subtitle('RV64M Instruction Subset (in addition to RV32M)')
  print_insts('mulw', 'divw', 'divuw', 'remw', 'remuw')
  print_subtitle('RV32A Instruction Subset')
  print_insts('amoadd.w', 'amoswap.w', 'amoand.w', 'amoor.w')
  print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w')
  print_insts('lr.w', 'sc.w')
  print_footer(0)

  print_header()
  print_subtitle('RV64A Instruction Subset (in addition to RV32A)')
  print_insts('amoadd.d', 'amoswap.d', 'amoand.d', 'amoor.d')
  print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d')
  print_insts('lr.d', 'sc.d')
  print_subtitle('RV32F Instruction Subset')
  print_insts('flw', 'fsw')
  print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s', 'fmin.s', 'fmax.s')
  print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s')
  print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s')
  print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x')
  print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s')
  print_insts('feq.s', 'flt.s', 'fle.s')
  print_insts('mtfsr', 'mffsr')
  print_footer(0)

  print_header()
  print_subtitle('RV64F Instruction Subset (in addition to RV32F)')
  print_insts('fcvt.s.l', 'fcvt.s.lu')
  print_insts('fcvt.l.s', 'fcvt.lu.s')
  print_subtitle('RV32D Instruction Subset')
  print_insts('fld', 'fsd')
  print_insts('fadd.d', 'fsub.d', 'fmul.d', 'fdiv.d', 'fsqrt.d', 'fmin.d', 'fmax.d')
  print_insts('fmadd.d', 'fmsub.d', 'fnmsub.d', 'fnmadd.d')
  print_insts('fsgnj.d', 'fsgnjn.d', 'fsgnjx.d')
  print_insts('fcvt.d.w', 'fcvt.d.wu')
  print_insts('fcvt.w.d', 'fcvt.wu.d')
  print_insts('feq.d', 'flt.d', 'fle.d')
  print_subtitle('RV64D Instruction Subset (in addition to RV32D)')
  print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x')
  print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d')
  print_insts('fcvt.s.d', 'fcvt.d.s')
  print_footer(1)

def print_verilog_insn(name):
  s = "`define %-10s 32'b" % name.replace('.', '_').upper()
  for i in range(31, -1, -1):
    if yank(mask[name], i, 1):
      s = '%s%d' % (s, yank(match[name], i, 1))
    else:
      s = s + '?'
  print s

def make_verilog():
  print '/* Automatically generated by parse-opcodes */'
  for name in namelist:
    print_verilog_insn(name)

for line in sys.stdin:
  line = line.partition('#')
  tokens = line[0].split()

  if len(tokens) == 0:
    continue
  assert len(tokens) >= 2

  name = tokens[0]
  mymatch = 0
  mymask = 0
  cover = 0

  if not name in arguments.keys():
    arguments[name] = []

  for token in tokens[1:]:
    if len(token.split('=')) == 2:
      tokens = token.split('=')
      if len(tokens[0].split('..')) == 2:
        tmp = tokens[0].split('..')
        hi = int(tmp[0])
        lo = int(tmp[1])
        if hi <= lo:
          sys.exit("%s: bad range %d..%d" % (name,hi,lo))
      else:
        hi = lo = int(tokens[0])

      if tokens[1] != 'ignore':
        val = int(tokens[1], 0)
        if val >= (1 << (hi-lo+1)):
          sys.exit("%s: bad value %d for range %d..%d" % (name,val,hi,lo))
        mymatch = mymatch | (val << lo)
        mymask = mymask | ((1<<(hi+1))-(1<<lo))

      if cover & ((1<<(hi+1))-(1<<lo)):
        sys.exit("%s: overspecified" % name)
      cover = cover | ((1<<(hi+1))-(1<<lo))

    elif token in arglut:
      if cover & ((1<<(arglut[token][0]+1))-(1<<arglut[token][1])):
        sys.exit("%s: overspecified" % name)
      cover = cover | ((1<<(arglut[token][0]+1))-(1<<arglut[token][1]))
      arguments[name].append(token)

    else:
      sys.exit("%s: unknown token %s" % (name,token))

  if not (cover == 0xFFFFFFFF or cover == 0xFFFF):
    sys.exit("%s: not all bits are covered" % name)

  for name2,match2 in match.iteritems():
    if (match2 & mymask) == mymatch:
      sys.exit("%s and %s overlap" % (name,name2))

  mask[name] = mymask
  match[name] = mymatch
  namelist.append(name)

if sys.argv[1] == '-tex':
  make_latex_table()
elif sys.argv[1] == '-verilog':
  make_verilog()
elif sys.argv[1] == '-disasm':
  make_disasm_table(match,mask)
elif sys.argv[1] == '-isasim':
  make_isasim(match,mask)
else:
  assert 0