#!/usr/bin/python import math import sys import tokenize namelist = [] match = {} mask = {} pseudos = {} arguments = {} arglut = {} arglut['rd'] = (11,7) arglut['rs1'] = (19,15) arglut['rs2'] = (24,20) arglut['rs3'] = (31,27) arglut['aqrl'] = (26,25) arglut['pred'] = (27,24) arglut['succ'] = (23,20) arglut['rm'] = (14,12) arglut['imm20'] = (31,12) arglut['jimm20'] = (31,12) arglut['imm12'] = (31,20) arglut['imm12hi'] = (31,25) arglut['bimm12hi'] = (31,25) arglut['imm12lo'] = (11,7) arglut['bimm12lo'] = (11,7) arglut['zimm'] = (19,15) arglut['shamt'] = (25,20) arglut['shamtw'] = (24,20) arglut['vseglen'] = (31,29) causes = [ (0x00, 'misaligned fetch'), (0x01, 'fault fetch'), (0x02, 'illegal instruction'), (0x03, 'breakpoint'), (0x04, 'misaligned load'), (0x05, 'fault load'), (0x06, 'misaligned store'), (0x07, 'fault store'), (0x08, 'user_ecall'), (0x09, 'supervisor_ecall'), (0x0A, 'hypervisor_ecall'), (0x0B, 'machine_ecall'), ] csrs = [ # Standard User R/W (0x001, 'fflags'), (0x002, 'frm'), (0x003, 'fcsr'), # Standard User RO (0xC00, 'cycle'), (0xC01, 'time'), (0xC02, 'instret'), # Nonstandard User R/W (0x0C0, 'stats'), # Nonstandard User RO (0xCC0, 'uarch0'), (0xCC1, 'uarch1'), (0xCC2, 'uarch2'), (0xCC3, 'uarch3'), (0xCC4, 'uarch4'), (0xCC5, 'uarch5'), (0xCC6, 'uarch6'), (0xCC7, 'uarch7'), (0xCC8, 'uarch8'), (0xCC9, 'uarch9'), (0xCCA, 'uarch10'), (0xCCB, 'uarch11'), (0xCCC, 'uarch12'), (0xCCD, 'uarch13'), (0xCCE, 'uarch14'), (0xCCF, 'uarch15'), # Standard Supervisor R/W (0x100, 'sstatus'), (0x101, 'stvec'), (0x104, 'sie'), (0x140, 'sscratch'), (0x141, 'sepc'), (0x144, 'sip'), (0x180, 'sptbr'), (0x181, 'sasid'), # Standard Supervisor R/W Shadows of User RO (0x900, 'cyclew'), (0x901, 'timew'), (0x902, 'instretw'), # Standard Supervisor RO (0xD01, 'stime'), (0xD42, 'scause'), (0xD43, 'sbadaddr'), # Standard Hypervisor R/W Shadows of Supervisor RO (0xA01, 'stimew'), # Standard Machine R/W (0x300, 'mstatus'), (0x301, 'mtvec'), (0x302, 'mtdeleg'), (0x304, 'mie'), (0x321, 'mtimecmp'), (0x340, 'mscratch'), (0x341, 'mepc'), (0x342, 'mcause'), (0x343, 'mbadaddr'), (0x344, 'mip'), (0x701, 'mtime'), # Standard Machine RO (0xF00, 'mcpuid'), (0xF01, 'mimpid'), (0xF10, 'mhartid'), # Nonstandard Machine R/W (0x780, 'mtohost'), (0x781, 'mfromhost'), (0x782, 'mreset'), (0x783, 'mipi'), (0x784, 'miobase'), ] csrs32 = [ # Standard User RO (0xC80, 'cycleh'), (0xC81, 'timeh'), (0xC82, 'instreth'), # Standard Supervisor R/W Shadows of User RO (0x980, 'cyclehw'), (0x981, 'timehw'), (0x982, 'instrethw'), # Standard Supervisor RO (0xD81, 'stimeh'), # Standard Hypervisor R/W Shadows of Supervisor RO (0xA81, 'stimehw'), # Standard Machine R/W (0x361, 'mtimecmph'), (0x741, 'mtimeh'), ] opcode_base = 0 opcode_size = 7 funct_base = 12 funct_size = 3 def binary(n, digits=0): rep = bin(n)[2:] return rep if digits == 0 else ('0' * (digits - len(rep))) + rep def make_c(match,mask): print '/* Automatically generated by parse-opcodes */' print '#ifndef RISCV_ENCODING_H' print '#define RISCV_ENCODING_H' for name in namelist: name2 = name.upper().replace('.','_') print '#define MATCH_%s %s' % (name2, hex(match[name])) print '#define MASK_%s %s' % (name2, hex(mask[name])) for num, name in csrs+csrs32: print '#define CSR_%s %s' % (name.upper(), hex(num)) for num, name in causes: print '#define CAUSE_%s %s' % (name.upper().replace(' ', '_'), hex(num)) print '#endif' print '#ifdef DECLARE_INSN' for name in namelist: name2 = name.replace('.','_') print 'DECLARE_INSN(%s, MATCH_%s, MASK_%s)' % (name2, name2.upper(), name2.upper()) print '#endif' print '#ifdef DECLARE_CSR' for num, name in csrs+csrs32: print 'DECLARE_CSR(%s, CSR_%s)' % (name, name.upper()) print '#endif' print '#ifdef DECLARE_CAUSE' for num, name in causes: print 'DECLARE_CAUSE("%s", CAUSE_%s)' % (name, name.upper().replace(' ', '_')) print '#endif' def yank(num,start,len): return (num >> start) & ((1 << len) - 1) def str_arg(arg0,name,match,arguments): if arg0 in arguments: return name or arg0 else: start = arglut[arg0][1] len = arglut[arg0][0] - arglut[arg0][1] + 1 return binary(yank(match,start,len),len) def str_inst(name,arguments): ret = name.replace('.rv32','').upper() + ' ' if 'imm12hi' in arguments and 'imm12lo' in arguments: arguments.remove('imm12hi') arguments.remove('imm12lo') arguments.append('imm') if 'bimm12hi' in arguments and 'bimm12lo' in arguments: arguments.remove('bimm12hi') arguments.remove('bimm12lo') arguments.append('imm') if name[:3] == 'csr': arguments.remove('imm12') arguments.remove('rs1') arguments.append('csr') arguments.append('imm' if name[-1] == 'i' else 'rs1') if 'imm12' in arguments: arguments.remove('imm12') arguments.append('imm') if 'imm20' in arguments: arguments.remove('imm20') arguments.append('imm') if 'jimm20' in arguments: arguments.remove('jimm20') arguments.append('imm') if 'zimm' in arguments: arguments.remove('zimm') arguments.append('imm') if 'shamtw' in arguments: arguments.remove('shamtw') arguments.append('shamt') if 'aqrl' in arguments: arguments.remove('aqrl') if 'rm' in arguments: arguments.remove('rm') if 'pred' in arguments: arguments.remove('pred') if 'succ' in arguments: arguments.remove('succ') for idx in range(len(arguments)): ret = ret + arguments[idx] if idx != len(arguments)-1: ret = ret + ',' return ret def print_unimp_type(name,match,arguments): print """ & \\multicolumn{10}{|c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ '0'*32, \ 'UNIMP' \ ) def print_u_type(name,match,arguments): print """ & \\multicolumn{8}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('imm20','imm[31:12]',match,arguments), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_uj_type(name,match,arguments): print """ & \\multicolumn{8}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('jimm20','imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]',match,arguments), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_s_type(name,match,arguments): print """ & \\multicolumn{4}{|c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('imm12hi','imm[11:5]',match,arguments), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('imm12lo','imm[4:0]',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_sb_type(name,match,arguments): print """ & \\multicolumn{4}{|c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('bimm12hi','imm[12$\\vert$10:5]',match,arguments), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('bimm12lo','imm[4:1$\\vert$11]',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_i_type(name,match,arguments): print """ & \\multicolumn{6}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('imm12','imm[11:0]',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_csr_type(name,match,arguments): print """ & \\multicolumn{6}{|c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('imm12','csr',match,arguments), \ ('zimm' if name[-1] == 'i' else 'rs1'), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_ish_type(name,match,arguments): print """ & \\multicolumn{3}{|c|}{%s} & \\multicolumn{3}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ binary(yank(match,26,6),6), \ str_arg('shamt','shamt',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_ishw_type(name,match,arguments): print """ & \\multicolumn{4}{|c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ binary(yank(match,25,7),7), \ str_arg('shamtw','shamt',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_r_type(name,match,arguments): print """ & \\multicolumn{4}{|c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ binary(yank(match,25,7),7), \ str_arg('rs2','',match,arguments), \ 'zimm' in arguments and str_arg('zimm','imm[4:0]',match,arguments) or str_arg('rs1','',match,arguments), \ str_arg('rm','',match,arguments), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_r4_type(name,match,arguments): print """ & \\multicolumn{2}{|c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ str_arg('rs3','',match,arguments), \ binary(yank(match,25,2),2), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ str_arg('rm','',match,arguments), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_amo_type(name,match,arguments): print """ & \\multicolumn{2}{|c|}{%s} & \\multicolumn{1}{c|}{aq} & \\multicolumn{1}{c|}{rl} & \\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ binary(yank(match,27,5),5), \ str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_fence_type(name,match,arguments): print """ & \\multicolumn{2}{|c|}{%s} & \\multicolumn{3}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ binary(yank(match,28,4),4), \ str_arg('pred','pred',match,arguments), \ str_arg('succ','',match,arguments), \ str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_header(*types): print """ \\newpage \\begin{table}[p] \\begin{small} \\begin{center} \\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l} & & & & & & & & & & \\\\ & \\multicolumn{1}{l}{\\instbit{31}} & \\multicolumn{1}{r}{\\instbit{27}} & \\instbit{26} & \\instbit{25} & \\multicolumn{1}{l}{\\instbit{24}} & \\multicolumn{1}{r}{\\instbit{20}} & \\instbitrange{19}{15} & \\instbitrange{14}{12} & \\instbitrange{11}{7} & \\instbitrange{6}{0} \\\\ \\cline{2-11} """ if 'r' in types: print """ & \\multicolumn{4}{|c|}{funct7} & \\multicolumn{2}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & \\multicolumn{1}{c|}{funct3} & \\multicolumn{1}{c|}{rd} & \\multicolumn{1}{c|}{opcode} & R-type \\\\ \\cline{2-11} """ if 'r4' in types: print """ & \\multicolumn{2}{|c|}{rs3} & \\multicolumn{2}{c|}{funct2} & \\multicolumn{2}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & \\multicolumn{1}{c|}{funct3} & \\multicolumn{1}{c|}{rd} & \\multicolumn{1}{c|}{opcode} & R4-type \\\\ \\cline{2-11} """ if 'i' in types: print """ & \\multicolumn{6}{|c|}{imm[11:0]} & \\multicolumn{1}{c|}{rs1} & \\multicolumn{1}{c|}{funct3} & \\multicolumn{1}{c|}{rd} & \\multicolumn{1}{c|}{opcode} & I-type \\\\ \\cline{2-11} """ if 's' in types: print """ & \\multicolumn{4}{|c|}{imm[11:5]} & \\multicolumn{2}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & \\multicolumn{1}{c|}{funct3} & \\multicolumn{1}{c|}{imm[4:0]} & \\multicolumn{1}{c|}{opcode} & S-type \\\\ \\cline{2-11} """ if 'sb' in types: print """ & \\multicolumn{4}{|c|}{imm[12$\\vert$10:5]} & \\multicolumn{2}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & \\multicolumn{1}{c|}{funct3} & \\multicolumn{1}{c|}{imm[4:1$\\vert$11]} & \\multicolumn{1}{c|}{opcode} & SB-type \\\\ \\cline{2-11} """ if 'u' in types: print """ & \\multicolumn{8}{|c|}{imm[31:12]} & \\multicolumn{1}{c|}{rd} & \\multicolumn{1}{c|}{opcode} & U-type \\\\ \\cline{2-11} """ if 'uj' in types: print """ & \\multicolumn{8}{|c|}{imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]} & \\multicolumn{1}{c|}{rd} & \\multicolumn{1}{c|}{opcode} & UJ-type \\\\ \\cline{2-11} """ def print_subtitle(title): print """ & \\multicolumn{10}{c}{} & \\\\ & \\multicolumn{10}{c}{\\bf %s} & \\\\ \\cline{2-11} """ % title def print_footer(caption=''): print """ \\end{tabular} \\end{center} \\end{small} %s \\label{instr-table} \\end{table} """ % caption def print_inst(n): is_system = (match[n] & 0x7f) == (match['scall'] & 0x7f) if n == 'fence' or n == 'fence.i': print_fence_type(n, match[n], arguments[n]) elif 'aqrl' in arguments[n]: print_amo_type(n, match[n], arguments[n]) elif 'shamt' in arguments[n]: print_ish_type(n, match[n], arguments[n]) elif 'shamtw' in arguments[n]: print_ishw_type(n, match[n], arguments[n]) elif 'imm20' in arguments[n]: print_u_type(n, match[n], arguments[n]) elif 'jimm20' in arguments[n]: print_uj_type(n, match[n], arguments[n]) elif is_system and n[:3] == 'csr': print_csr_type(n, match[n], arguments[n]) elif 'imm12' in arguments[n] or is_system: print_i_type(n, match[n], arguments[n]) elif 'imm12hi' in arguments[n]: print_s_type(n, match[n], arguments[n]) elif 'bimm12hi' in arguments[n]: print_sb_type(n, match[n], arguments[n]) elif 'rs3' in arguments[n]: print_r4_type(n, match[n], arguments[n]) else: print_r_type(n, match[n], arguments[n]) def print_insts(*names): for n in names: print_inst(n) def make_supervisor_latex_table(): print_header('i') print_subtitle('Instructions to Access CSRs') print_insts('csrrw', 'csrrs', 'csrrc') print_insts('csrrwi', 'csrrsi', 'csrrci') print_subtitle('Instructions to Change Privilege Level') print_insts('ecall', 'ebreak', 'eret') print_subtitle('Trap-Redirection Instructions') print_insts('mrts', 'mrth', 'hrts') print_subtitle('Interrupt-Management Instructions') print_insts('wfi') print_subtitle('Memory-Management Instructions') print_insts('sfence.vm') print_footer('\\caption{RISC-V Privileged Instructions}') def make_latex_table(): print_header('r','i','s','sb','u','uj') print_subtitle('RV32I Base Instruction Set') print_insts('lui', 'auipc') print_insts('jal', 'jalr', 'beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu') print_insts('lb', 'lh', 'lw', 'lbu', 'lhu', 'sb', 'sh', 'sw') print_insts('addi', 'slti', 'sltiu', 'xori', 'ori', 'andi', 'slli.rv32', 'srli.rv32', 'srai.rv32') print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and') print_insts('fence', 'fence.i') print_insts('scall', 'sbreak') print_insts('rdcycle', 'rdcycleh') print_insts('rdtime', 'rdtimeh') print_insts('rdinstret', 'rdinstreth') print_footer() print_header('r','a','i','s') print_subtitle('RV64I Base Instruction Set (in addition to RV32I)') print_insts('lwu', 'ld', 'sd') print_insts('slli', 'srli', 'srai') print_insts('addiw', 'slliw', 'srliw', 'sraiw') print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw') print_subtitle('RV32M Standard Extension') print_insts('mul', 'mulh', 'mulhsu', 'mulhu') print_insts('div', 'divu', 'rem', 'remu') print_subtitle('RV64M Standard Extension (in addition to RV32M)') print_insts('mulw', 'divw', 'divuw', 'remw', 'remuw') print_subtitle('RV32A Standard Extension') print_insts('lr.w', 'sc.w') print_insts('amoswap.w') print_insts('amoadd.w', 'amoxor.w', 'amoand.w', 'amoor.w') print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w') print_footer() print_header('r','r4','i','s') print_subtitle('RV64A Standard Extension (in addition to RV32A)') print_insts('lr.d', 'sc.d') print_insts('amoswap.d') print_insts('amoadd.d', 'amoxor.d', 'amoand.d', 'amoor.d') print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d') print_subtitle('RV32F Standard Extension') print_insts('flw', 'fsw') print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s') print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s') print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s', 'fmin.s', 'fmax.s') print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s') print_insts('feq.s', 'flt.s', 'fle.s', 'fclass.s') print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x') print_insts('frcsr', 'frrm', 'frflags') print_insts('fscsr', 'fsrm', 'fsflags', 'fsrmi', 'fsflagsi') print_footer() print_header('r','r4','i','s') print_subtitle('RV64F Standard Extension (in addition to RV32F)') print_insts('fcvt.l.s', 'fcvt.lu.s') print_insts('fcvt.s.l', 'fcvt.s.lu') print_subtitle('RV32D Standard Extension') print_insts('fld', 'fsd') print_insts('fmadd.d', 'fmsub.d', 'fnmsub.d', 'fnmadd.d') print_insts('fadd.d', 'fsub.d', 'fmul.d', 'fdiv.d', 'fsqrt.d') print_insts('fsgnj.d', 'fsgnjn.d', 'fsgnjx.d', 'fmin.d', 'fmax.d') print_insts('fcvt.s.d', 'fcvt.d.s') print_insts('feq.d', 'flt.d', 'fle.d', 'fclass.d') print_insts('fcvt.w.d', 'fcvt.wu.d') print_insts('fcvt.d.w', 'fcvt.d.wu') print_subtitle('RV64D Standard Extension (in addition to RV32D)') print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d') print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x') print_footer('\\caption{Instruction listing for RISC-V}') def print_chisel_insn(name): s = " def %-18s = BitPat(\"b" % name.replace('.', '_').upper() for i in range(31, -1, -1): if yank(mask[name], i, 1): s = '%s%d' % (s, yank(match[name], i, 1)) else: s = s + '?' print s + "\")" def make_chisel(): print '/* Automatically generated by parse-opcodes */' print 'object Instructions {' for name in namelist: print_chisel_insn(name) print '}' print 'object Causes {' for num, name in causes: print ' val %s = %s' % (name.lower().replace(' ', '_'), hex(num)) print ' val all = {' print ' val res = collection.mutable.ArrayBuffer[Int]()' for num, name in causes: print ' res += %s' % (name.lower().replace(' ', '_')) print ' res.toArray' print ' }' print '}' print 'object CSRs {' for num, name in csrs+csrs32: print ' val %s = %s' % (name, hex(num)) print ' val all = {' print ' val res = collection.mutable.ArrayBuffer[Int]()' for num, name in csrs: print ' res += %s' % (name) print ' res.toArray' print ' }' print ' val all32 = {' print ' val res = collection.mutable.ArrayBuffer(all:_*)' for num, name in csrs32: print ' res += %s' % (name) print ' res.toArray' print ' }' print '}' def signed(value, width): if 0 <= value < (1<<(width-1)): return value else: return value - (1<= 2 name = tokens[0] pseudo = name[0] == '@' if pseudo: name = name[1:] mymatch = 0 mymask = 0 cover = 0 if not name in arguments.keys(): arguments[name] = [] for token in tokens[1:]: if len(token.split('=')) == 2: tokens = token.split('=') if len(tokens[0].split('..')) == 2: tmp = tokens[0].split('..') hi = int(tmp[0]) lo = int(tmp[1]) if hi <= lo: sys.exit("%s: bad range %d..%d" % (name,hi,lo)) else: hi = lo = int(tokens[0]) if tokens[1] != 'ignore': val = int(tokens[1], 0) if val >= (1 << (hi-lo+1)): sys.exit("%s: bad value %d for range %d..%d" % (name,val,hi,lo)) mymatch = mymatch | (val << lo) mymask = mymask | ((1<<(hi+1))-(1<