# format of a line in this file: # # # is given by specifying one or more range/value pairs: # highbit..lowbit=value (e.g. 6..0=0x45 9..7=0x0) # # is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw unimp 31..0=0 j imm25 6..0=0x60 jal imm25 6..0=0x61 jalr.c rd rs1 imm12 9..7=0 6..0=0x62 jalr.r rd rs1 imm12 9..7=1 6..0=0x62 jalr.j rd rs1 imm12 9..7=2 6..0=0x62 beq imm12hi rs1 rs2 imm12lo 9..7=0 6..0=0x63 bne imm12hi rs1 rs2 imm12lo 9..7=1 6..0=0x63 blt imm12hi rs1 rs2 imm12lo 9..7=4 6..0=0x63 bge imm12hi rs1 rs2 imm12lo 9..7=5 6..0=0x63 bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..0=0x63 bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..0=0x63 lui rd imm20 6..0=0x71 addi rd rs1 imm12 9..7=0 6..0=0x74 slti rd rs1 imm12 9..7=2 6..0=0x74 sltiu rd rs1 imm12 9..7=3 6..0=0x74 andi rd rs1 imm12 9..7=4 6..0=0x74 ori rd rs1 imm12 9..7=5 6..0=0x74 xori rd rs1 imm12 9..7=6 6..0=0x74 slli rd rs1 shamt 15..10=1 9..7=7 6..0=0x74 srli rd rs1 shamt 15..10=2 9..7=7 6..0=0x74 srai rd rs1 shamt 15..10=3 9..7=7 6..0=0x74 add rd rs1 rs2 16..10=0 9..7=0 6..0=0x75 sub rd rs1 rs2 16..10=1 9..7=0 6..0=0x75 slt rd rs1 rs2 16..10=2 9..7=0 6..0=0x75 sltu rd rs1 rs2 16..10=3 9..7=0 6..0=0x75 and rd rs1 rs2 16..10=4 9..7=0 6..0=0x75 or rd rs1 rs2 16..10=5 9..7=0 6..0=0x75 xor rd rs1 rs2 16..10=6 9..7=0 6..0=0x75 nor rd rs1 rs2 16..10=7 9..7=0 6..0=0x75 sll rd rs1 rs2 16=0 15..10=1 9..7=7 6..0=0x75 srl rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x75 sra rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x75 mul rd rs1 rs2 16..10=0 9..7=1 6..0=0x75 mulh rd rs1 rs2 16..10=2 9..7=1 6..0=0x75 mulhu rd rs1 rs2 16..10=3 9..7=1 6..0=0x75 div rd rs1 rs2 16..10=4 9..7=1 6..0=0x75 divu rd rs1 rs2 16..10=5 9..7=1 6..0=0x75 rem rd rs1 rs2 16..10=6 9..7=1 6..0=0x75 remu rd rs1 rs2 16..10=7 9..7=1 6..0=0x75 addiw rd rs1 imm12 9..7=0 6..0=0x76 slliw rd rs1 21=0 shamtw 15..10=1 9..7=7 6..0=0x76 srliw rd rs1 21=0 shamtw 15..10=2 9..7=7 6..0=0x76 sraiw rd rs1 21=0 shamtw 15..10=3 9..7=7 6..0=0x76 addw rd rs1 rs2 16..10=0 9..7=0 6..0=0x77 subw rd rs1 rs2 16..10=1 9..7=0 6..0=0x77 sllw rd rs1 rs2 16=0 15..10=1 9..7=7 6..0=0x77 srlw rd rs1 rs2 16=0 15..10=2 9..7=7 6..0=0x77 sraw rd rs1 rs2 16=0 15..10=3 9..7=7 6..0=0x77 mulw rd rs1 rs2 16..10=0 9..7=1 6..0=0x77 mulhw rd rs1 rs2 16..10=2 9..7=1 6..0=0x77 mulhuw rd rs1 rs2 16..10=3 9..7=1 6..0=0x77 divw rd rs1 rs2 16..10=4 9..7=1 6..0=0x77 divuw rd rs1 rs2 16..10=5 9..7=1 6..0=0x77 remw rd rs1 rs2 16..10=6 9..7=1 6..0=0x77 remuw rd rs1 rs2 16..10=7 9..7=1 6..0=0x77 lb rd rs1 imm12 9..7=0 6..0=0x78 lh rd rs1 imm12 9..7=1 6..0=0x78 lw rd rs1 imm12 9..7=2 6..0=0x78 ld rd rs1 imm12 9..7=3 6..0=0x78 lbu rd rs1 imm12 9..7=4 6..0=0x78 lhu rd rs1 imm12 9..7=5 6..0=0x78 lwu rd rs1 imm12 9..7=6 6..0=0x78 synci 31..27=0 rs1 imm12 9..7=7 6..0=0x78 # NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c # and elfxx-mips.c to detect them. this is a hack to handle the split immed. # just open up those files and search for MATCH_SW; should be obvious. sb imm12hi rs1 rs2 imm12lo 9..7=0 6..0=0x79 sh imm12hi rs1 rs2 imm12lo 9..7=1 6..0=0x79 sw imm12hi rs1 rs2 imm12lo 9..7=2 6..0=0x79 sd imm12hi rs1 rs2 imm12lo 9..7=3 6..0=0x79 amow.add rd rs1 rs2 16..10=0 9..7=2 6..0=0x7A amow.swap rd rs1 rs2 16..10=1 9..7=2 6..0=0x7A amow.and rd rs1 rs2 16..10=2 9..7=2 6..0=0x7A amow.or rd rs1 rs2 16..10=3 9..7=2 6..0=0x7A amow.min rd rs1 rs2 16..10=4 9..7=2 6..0=0x7A amow.max rd rs1 rs2 16..10=5 9..7=2 6..0=0x7A amow.minu rd rs1 rs2 16..10=6 9..7=2 6..0=0x7A amow.maxu rd rs1 rs2 16..10=7 9..7=2 6..0=0x7A amo.add rd rs1 rs2 16..10=0 9..7=3 6..0=0x7A amo.swap rd rs1 rs2 16..10=1 9..7=3 6..0=0x7A amo.and rd rs1 rs2 16..10=2 9..7=3 6..0=0x7A amo.or rd rs1 rs2 16..10=3 9..7=3 6..0=0x7A amo.min rd rs1 rs2 16..10=4 9..7=3 6..0=0x7A amo.max rd rs1 rs2 16..10=5 9..7=3 6..0=0x7A amo.minu rd rs1 rs2 16..10=6 9..7=3 6..0=0x7A amo.maxu rd rs1 rs2 16..10=7 9..7=3 6..0=0x7A rdnpc rd 26..17=0 16..10=0 9..7=0 6..0=0x7B mfcr rd 26..22=0 rs2 16..10=0 9..7=1 6..0=0x7B mtcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..0=0x7B sync 31..17=0 16..10=0 9..7=2 6..0=0x7B syscall 31..22=0 imm12 9..7=3 6..0=0x7B ei rd 26..17=0 16..10=0 9..7=0 6..0=0x6B di rd 26..17=0 16..10=1 9..7=0 6..0=0x6B mfpcr rd 26..22=0 rs2 16..10=0 9..7=1 6..0=0x6B mtpcr 31..27=0 rs1 rs2 16..10=1 9..7=1 6..0=0x6B eret 31..17=0 16..10=0 9..7=2 6..0=0x6B # 0x7C-0x7F are reserved for >32b instructions add.s rd rs1 rs2 16..12=0 rm 8..7=0 6..0=0x6A sub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..0=0x6A mul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..0=0x6A div.s rd rs1 rs2 16..12=3 rm 8..7=0 6..0=0x6A sqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..0=0x6A sgninj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..0=0x6A sgninjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..0=0x6A sgnmul.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..0=0x6A add.d rd rs1 rs2 16..12=0x0 rm 8..7=3 6..0=0x6A sub.d rd rs1 rs2 16..12=0x1 rm 8..7=3 6..0=0x6A mul.d rd rs1 rs2 16..12=0x2 rm 8..7=3 6..0=0x6A div.d rd rs1 rs2 16..12=0x3 rm 8..7=3 6..0=0x6A sqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=3 6..0=0x6A sgninj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=3 6..0=0x6A sgninjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=3 6..0=0x6A sgnmul.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=3 6..0=0x6A cvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..0=0x6A cvtu.l.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..0=0x6A cvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..0=0x6A cvtu.w.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..0=0x6A cvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=3 6..0=0x6A cvtu.l.d rd rs1 21..17=0 16..12=0x9 rm 8..7=3 6..0=0x6A cvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=3 6..0=0x6A cvtu.w.d rd rs1 21..17=0 16..12=0xB rm 8..7=3 6..0=0x6A cvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..0=0x6A cvtu.s.l rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..0=0x6A cvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..0=0x6A cvtu.s.w rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..0=0x6A cvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=3 6..0=0x6A cvtu.d.l rd rs1 21..17=0 16..12=0xD rm 8..7=3 6..0=0x6A cvt.d.w rd rs1 21..17=0 16..12=0xE 11..9=0 8..7=3 6..0=0x6A cvtu.d.w rd rs1 21..17=0 16..12=0xF 11..9=0 8..7=3 6..0=0x6A cvt.s.d rd rs1 21..17=0 16..12=0x13 rm 8..7=0 6..0=0x6A cvt.d.s rd rs1 21..17=0 16..12=0x10 11..9=0 8..7=3 6..0=0x6A c.eq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..0=0x6A c.lt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..0=0x6A c.le.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..0=0x6A c.eq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=3 6..0=0x6A c.lt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=3 6..0=0x6A c.le.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=3 6..0=0x6A mff.s rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=0 6..0=0x6A mff.d rd 26..22=0 rs2 16..12=0x18 11..9=2 8..7=3 6..0=0x6A mffl.d rd 26..22=0 rs2 16..12=0x19 11..9=2 8..7=3 6..0=0x6A mffh.d rd 26..22=0 rs2 16..12=0x1A 11..9=2 8..7=3 6..0=0x6A mtf.s rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=0 6..0=0x6A mtf.d rd rs1 21..17=0 16..12=0x1C 11..9=2 8..7=3 6..0=0x6A mtflh.d rd rs1 rs2 16..12=0x1C 11..9=3 8..7=3 6..0=0x6A l.s rd rs1 imm12 9..7=2 6..0=0x68 l.d rd rs1 imm12 9..7=3 6..0=0x68 s.s imm12hi rs1 rs2 imm12lo 9..7=2 6..0=0x69 s.d imm12hi rs1 rs2 imm12lo 9..7=3 6..0=0x69 madd.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6C msub.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6D nmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6E nmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..0=0x6F madd.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6C msub.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6D nmsub.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6E nmadd.d rd rs1 rs2 rs3 rm 8..7=3 6..0=0x6F