From f1f72abca9f7511990c476d326c864c96a758732 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 19 Jun 2011 19:18:54 -0700 Subject: [riscv-isa-run] code cleanup; added README --- parse-opcodes | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'parse-opcodes') diff --git a/parse-opcodes b/parse-opcodes index 707947e..26b8779 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -85,7 +85,7 @@ def make_disasm_table(match,mask): print '#define MATCH_%s %s' % (name2, hex(match)) print '#define MASK_%s %s' % (name2, hex(mask[name])) -def make_switch(match, mask): +def make_isasim(match, mask): for name in match.iterkeys(): name2 = name.replace('.','_') print 'DECLARE_INSN(%s, 0x%x, 0x%x)' % (name2, match[name], mask[name]) @@ -683,6 +683,7 @@ def print_verilog_r_type(name,match,arguments): ) def make_verilog(): + print '/* Automatically generated by parse-opcodes */' for name in namelist: if types[name] == 0: print_verilog_unimp_type(name,match[name],arguments[name]) @@ -784,7 +785,7 @@ elif sys.argv[1] == '-verilog': make_verilog() elif sys.argv[1] == '-disasm': make_disasm_table(match,mask) -elif sys.argv[1] == '-switch': - make_switch(match,mask) +elif sys.argv[1] == '-isasim': + make_isasim(match,mask) else: assert 0 -- cgit v1.2.3