From dd6b8266f1d06a0e5acbbed4e8a5fcd3fcd2fcd1 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 4 Apr 2011 01:16:10 -0700 Subject: [opcodes,pk,sim,xcc] add vector mem instructions --- opcodes | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'opcodes') diff --git a/opcodes b/opcodes index 8e5c943..a92a8ac 100644 --- a/opcodes +++ b/opcodes @@ -203,3 +203,41 @@ fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3 fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 + +ld.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lw.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lh.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lb.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbu.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 + +sd.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +sw.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +sh.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=1 6..2=0x02 1..0=3 +sb.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=0 6..2=0x02 1..0=3 + +fld.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +flw.v rd rs1 21..17=0 16..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 + +fsd.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +fsw.v 31..27=0 rs1 21..17=0 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +ldst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +lwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +lwust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +lhst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +lhust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +lbst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +lbust.v rd rs1 rs2 16..12=0 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3 + +sdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +swst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +shst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=1 6..2=0x02 1..0=3 +sbst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=0 6..2=0x02 1..0=3 + +fldst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +flwst.v rd rs1 rs2 16..12=0 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 + +fsdst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +fswst.v 31..27=0 rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 -- cgit v1.2.3