From 05e0d24dc582a92eae1809451833d5c76335b81a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 13 May 2011 14:56:57 -0700 Subject: tweaked encoding of rdcycle & cousins --- opcodes | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'opcodes') diff --git a/opcodes b/opcodes index 96d8eea..82eafc9 100644 --- a/opcodes +++ b/opcodes @@ -107,8 +107,11 @@ amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3 fence.i rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3 fence rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3 -syscall 31..27=0 26..22=0 21..17=0 16..7=0 6..2=0x1D 1..0=3 -break 31..27=0 26..22=0 21..17=0 16..7=1 6..2=0x1D 1..0=3 +syscall 31..27=0 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1D 1..0=3 +break 31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x1D 1..0=3 +rdcycle rd 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3 +rdtime rd 26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3 +rdinstret rd 26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3 # vector fence instructions fence.l.v rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3 @@ -164,11 +167,11 @@ fcvt.s.wu rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..2=0x14 1..0=3 fcvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=1 6..2=0x14 1..0=3 fcvt.d.lu rd rs1 21..17=0 16..12=0xD rm 8..7=1 6..2=0x14 1..0=3 -fcvt.d.w rd rs1 21..17=0 16..12=0xE 11..9=0 8..7=1 6..2=0x14 1..0=3 -fcvt.d.wu rd rs1 21..17=0 16..12=0xF 11..9=0 8..7=1 6..2=0x14 1..0=3 +fcvt.d.w rd rs1 21..17=0 16..12=0xE rm 8..7=1 6..2=0x14 1..0=3 +fcvt.d.wu rd rs1 21..17=0 16..12=0xF rm 8..7=1 6..2=0x14 1..0=3 fcvt.s.d rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3 -fcvt.d.s rd rs1 21..17=0 16..14=0x4 13..12=0 11..9=0 8..7=1 6..2=0x14 1..0=3 +fcvt.d.s rd rs1 21..17=0 16..14=0x4 13..12=0 rm 8..7=1 6..2=0x14 1..0=3 feq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3 flt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3 -- cgit v1.2.3