From 89daf14d5b338c2d603a76477dfdbe8211b5aac0 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Tue, 18 Mar 2014 14:39:07 -0700
Subject: Add rdcycleh etc. for RV32

---
 inst.chisel | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'inst.chisel')

diff --git a/inst.chisel b/inst.chisel
index efb1ba7..455ca08 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -255,6 +255,10 @@ object CSRs {
   val uarch13 = 0xccd
   val uarch14 = 0xcce
   val uarch15 = 0xccf
+  val counth = 0x586
+  val cycleh = 0xc80
+  val timeh = 0xc81
+  val instreth = 0xc82
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
     res += fflags
@@ -301,4 +305,12 @@ object CSRs {
     res += uarch15
     res.toArray
   }
+  val all32 = {
+    val res = collection.mutable.ArrayBuffer(all:_*)
+    res += counth
+    res += cycleh
+    res += timeh
+    res += instreth
+    res.toArray
+  }
 }
-- 
cgit v1.2.3