From 43ca48c7d1ff67af4286a93185fc83f75be4760f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 Mar 2015 17:35:30 -0700 Subject: Update to new privileged spec --- inst.chisel | 120 +++++++++++++++++++++++++++++++++--------------------------- 1 file changed, 66 insertions(+), 54 deletions(-) (limited to 'inst.chisel') diff --git a/inst.chisel b/inst.chisel index b9454d3..a4f876b 100644 --- a/inst.chisel +++ b/inst.chisel @@ -88,7 +88,11 @@ object Instructions { def SC_D = Bits("b00011????????????011?????0101111") def SCALL = Bits("b00000000000000000000000001110011") def SBREAK = Bits("b00000000000100000000000001110011") - def SRET = Bits("b10000000000000000000000001110011") + def SRET = Bits("b00010000001000000000000001110011") + def SFENCE_VM = Bits("b000100000100?????000000001110011") + def MCALL = Bits("b00100000000000000000000001110011") + def MRET = Bits("b00110000001000000000000001110011") + def MRTS = Bits("b00110000100100000000000001110011") def CSRRW = Bits("b?????????????????001?????1110011") def CSRRS = Bits("b?????????????????010?????1110011") def CSRRC = Bits("b?????????????????011?????1110011") @@ -186,29 +190,27 @@ object Causes { val misaligned_fetch = 0x0 val fault_fetch = 0x1 val illegal_instruction = 0x2 - val privileged_instruction = 0x3 - val fp_disabled = 0x4 - val syscall = 0x6 + val scall = 0x4 + val hcall = 0x5 + val mcall = 0x6 val breakpoint = 0x7 val misaligned_load = 0x8 - val misaligned_store = 0x9 - val fault_load = 0xa + val fault_load = 0x9 + val misaligned_store = 0xa val fault_store = 0xb - val accelerator_disabled = 0xc val all = { val res = collection.mutable.ArrayBuffer[Int]() res += misaligned_fetch res += fault_fetch res += illegal_instruction - res += privileged_instruction - res += fp_disabled - res += syscall + res += scall + res += hcall + res += mcall res += breakpoint res += misaligned_load - res += misaligned_store res += fault_load + res += misaligned_store res += fault_store - res += accelerator_disabled res.toArray } } @@ -216,29 +218,10 @@ object CSRs { val fflags = 0x1 val frm = 0x2 val fcsr = 0x3 - val stats = 0xc0 - val sup0 = 0x500 - val sup1 = 0x501 - val epc = 0x502 - val badvaddr = 0x503 - val ptbr = 0x504 - val asid = 0x505 - val count = 0x506 - val compare = 0x507 - val evec = 0x508 - val cause = 0x509 - val status = 0x50a - val hartid = 0x50b - val impl = 0x50c - val fatc = 0x50d - val send_ipi = 0x50e - val clear_ipi = 0x50f - val reset = 0x51d - val tohost = 0x51e - val fromhost = 0x51f val cycle = 0xc00 val time = 0xc01 val instret = 0xc02 + val stats = 0xc0 val uarch0 = 0xcc0 val uarch1 = 0xcc1 val uarch2 = 0xcc2 @@ -255,38 +238,43 @@ object CSRs { val uarch13 = 0xccd val uarch14 = 0xcce val uarch15 = 0xccf - val counth = 0x586 + val sstatus = 0x100 + val stvec = 0x101 + val stimecmp = 0x121 + val sscratch = 0x140 + val sepc = 0x141 + val sptbr = 0x188 + val sasid = 0x189 + val scycle = 0x900 + val stime = 0x901 + val sinstret = 0x902 + val scause = 0xd40 + val sbadaddr = 0xd41 + val mstatus = 0x300 + val mscratch = 0x340 + val mepc = 0x341 + val mcause = 0x342 + val mbadaddr = 0x343 + val reset = 0x780 + val tohost = 0x781 + val fromhost = 0x782 + val send_ipi = 0x783 + val hartid = 0xfc0 val cycleh = 0xc80 val timeh = 0xc81 val instreth = 0xc82 + val scycleh = 0x980 + val stimeh = 0x981 + val sinstreth = 0x982 val all = { val res = collection.mutable.ArrayBuffer[Int]() res += fflags res += frm res += fcsr - res += stats - res += sup0 - res += sup1 - res += epc - res += badvaddr - res += ptbr - res += asid - res += count - res += compare - res += evec - res += cause - res += status - res += hartid - res += impl - res += fatc - res += send_ipi - res += clear_ipi - res += reset - res += tohost - res += fromhost res += cycle res += time res += instret + res += stats res += uarch0 res += uarch1 res += uarch2 @@ -303,14 +291,38 @@ object CSRs { res += uarch13 res += uarch14 res += uarch15 + res += sstatus + res += stvec + res += stimecmp + res += sscratch + res += sepc + res += sptbr + res += sasid + res += scycle + res += stime + res += sinstret + res += scause + res += sbadaddr + res += mstatus + res += mscratch + res += mepc + res += mcause + res += mbadaddr + res += reset + res += tohost + res += fromhost + res += send_ipi + res += hartid res.toArray } val all32 = { val res = collection.mutable.ArrayBuffer(all:_*) - res += counth res += cycleh res += timeh res += instreth + res += scycleh + res += stimeh + res += sinstreth res.toArray } } -- cgit v1.2.3